Low Power Circuit Design for Dynamic Comparator

摘要

The comparator is a crucial module in Analog-to-Digital Converters (ADC) design and Input Output circuits. In this design, a technique to diminish dynamic power of the comparator is proposed. The traditional latch circuit with two cross coupled inverters is modified. A comparable high-speed, energy-efficient N-MOS transistor is designed and used as input for both the preamplifier phase and latch phase. NMOS transistors are inherently superior to PMOS transistors in view of power consumption. A special clock circuit is designed to control two phases, namely the preamplifier phase and the latch phase. This clock circuit produces considerable benefits during the pre-amplification phase. The designed cross coupled circuit enhances the speed and reduces power consumption when compared with the conventional CMOS comparator. The proposed comparator is simulated in standard cadence 90nm technology. Simulation results shows that the proposed modified comparator design is suitable for high speed and low power application.