A low power media processor core performable CIF30fr/s MPEG4/H26x video codec

摘要

A architectural design of a media processor core optimized for MPEG4/H26× video codec targeting for mobile multimedia terminals[l1 is presented. The architecture consists of unique STMD (Single Instruction Multiple Data) processor, RISC-processor, VLC-processor, intelligent DMA controller. CIF 30frames/s MPEG4 Simple Profile video codec @ 100MHz is performed. Estimated dissipation is as low as 280mW. 300kgates and 16kBytes four port SRAM are contained on 12mm{sup}2 area using 0.18μm process technology. The combination of RISC-processor and SIMD-processor can also operate MPEG4 core profile (shape coding) that requires flexibility and performance.