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Digital System Design, Architectures, Methods and Tools, 2009. DSD '09
Digital System Design, Architectures, Methods and Tools, 2009. DSD '09
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1.
Architecture-Driven Synthesis of Reconfigurable Cells
机译:
架构驱动的可重构单元综合
作者:
Wolinski C.
;
Kuchcinski K.
;
Raffin E.
;
Charot F.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
constraint handling;
graph theory;
microprocessor chips;
reconfigurable architectures;
Media-Bench test suite;
architecture-driven synthesis;
constraint programming;
pattern merging problem;
reconfigurable cells;
run-time reconfigurable processor extension;
ASIP;
instruction selection;
reconfigurable computing;
scheduling;
2.
SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform
机译:
SIMD体系结构增强功能可提高2D离散小波变换的性能
作者:
Shahbahrami A.
;
Juurlink B.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
data flow graphs;
discrete wavelet transforms;
filtering theory;
floating point arithmetic;
image processing;
parallel processing;
2D discrete wavelet transform;
32-bit single-precision floating-point multiplications;
Daub-4 transform;
MAC;
SIMD architectural enhancements;
data flow graph;
data rearrangement instructions;
extended subword technique;
horizontal filtering;
lifting transform;
matrix register file;
time-consuming kernel;
vectorization;
vertical filtering;
DWT;
Parallelization;
SIMD Architectures;
3.
Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution
机译:
支持HSPA演进的并行Turbo解码的内存冲突分析和交织器设计
作者:
Asghar R.
;
Di Wu
;
Eilert J.
;
Liu D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
buffer circuits;
code division multiple access;
decoding;
interleaved codes;
parallel architectures;
turbo codes;
FIFO buffer;
HSPA;
SISO decoding;
WCDMA;
frequency 150 MHz;
high speed packet access;
interleaver design;
memory conflict analysis;
memory division;
parallel SISO blocks;
parallel turbo decoding;
preprocessing overhead;
segment based modulo computation;
stream misalignment;
Block interleaver;
Parallel interleaver;
UMTS;
4.
High Reliable Remote Terminal Unit for Space Applications
机译:
适用于太空应用的高可靠性远程终端单元
作者:
Guzman D.
;
Prieto M.
;
Garcia D.
;
Ruiz V.
;
Almena J.
;
Sanchez S.
;
Meziat D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
aerospace control;
controller area networks;
microcontrollers;
space vehicle electronics;
system-on-chip;
2.0 CAN controller;
80C32 microcontroller;
ADC interfaces;
SoC;
UART interface;
auto-check capabilities;
embedded generic firmware;
fault tolerance;
flight software;
general purpose digital I/O;
hardware redundancy;
high reliable remote terminal unit;
low power consumption;
satellites;
space applications;
spacecraft control system;
Field;
Remote Terminal Unit (RTU);
Satellite;
5.
GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations
机译:
时间相关的空气污染物传输方程的GPU加速求解器
作者:
Simek V.
;
Dvorak R.
;
Zboril F.
;
Drabek V.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Runge-Kutta methods;
air pollution;
cache storage;
computer graphic equipment;
environmental factors;
environmental science computing;
integration;
microprocessor chips;
partial differential equations;
storage management;
GPU accelerated solver;
GPU chip;
Runge-Kutta scheme;
advection-diffusion equation calculation;
commodity add-on card;
compute unified device architecture software framework;
general-purpose graphics processing unit;
memory management;
numerical integration;
partial differential equation;
pollutan;
6.
Survey of Test Data Compression Technique Emphasizing Code Based Schemes
机译:
强调基于代码的方案的测试数据压缩技术概述
作者:
Mehta U.
;
Dasgupta K.S.
;
Devashrayee N.M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
VLSI;
data compression;
fault diagnosis;
100X tester cycle reduction;
VLSI field;
code-based schemes;
coding theory;
data compression technique;
design complexity;
fault models;
standard stuck-at scan tests;
Automatic Test Equipment;
Code Based Data Compression;
FDR code;
Huffman Code;
Test Data Compression;
7.
xMAML: A Modeling Language for Dynamically Reconfigurable Architectures
机译:
xMAML:用于动态可重新配置体系结构的建模语言
作者:
Lallet J.
;
Pillement S.
;
Sentieys O.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
code division multiple access;
radio receivers;
reconfigurable architectures;
simulation languages;
system-on-chip;
WCDMA receiver;
dynamically reconfigurable architectures;
flexibility requirements;
high-level architecture description languages;
modeling language;
xMAML;
ADL;
dynamic reconfiguration;
8.
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm
机译:
基于片上网络范例的LDPC解码器的灵活架构
作者:
Vacca F.
;
Masera G.
;
Moussa H.
;
Baghdadi A.
;
Jezequel M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
flexible electronics;
network synthesis;
network-on-chip;
parity check codes;
LDPC decoders;
flexible architectures;
flexible low density parity check;
network on chip communication infrastructure;
LDPC;
NOC;
Network on Chip;
hardware implementation;
partially parallel decoder;
9.
Energy and Performance Model of a SPARC Leon3 Processor
机译:
SPARC Leon3处理器的能源和性能模型
作者:
Penolazzi S.
;
Bolognino L.
;
Hemani A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
instruction sets;
microprocessor chips;
system-on-chip;
SPARC Leon3 processor;
back-annotated gate-level netlist;
coarse-grain estimation;
data registers;
data switching activity;
fine-grain estimation;
instruction set simulation;
instruction-level characterization;
performance model;
processor energy model;
10.
Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization
机译:
基于局部宽度/成本最小化的多终端BDD启发式综合
作者:
Mikusek P.
;
Dvorak V.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Boolean functions;
binary decision diagrams;
cost reduction;
firmware;
minimisation;
table lookup;
Boolean variables;
firmware implementation;
heuristic synthesis;
integer-valued functions;
local width/cost minimization;
multiple output Boolean functions;
multiterminal binary decision diagrams;
LUT cascades;
functional decomposition;
incompletely specified functions;
iterative disjunctive decomposition;
multi-terminal BDDs;
11.
Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks
机译:
通过利用无线传感器和执行器网络中的异构性来满足延迟要求的功率感知
作者:
Borms J.
;
Steenhaut K.
;
Lemmens B.
;
Nowe A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
wireless sensor networks;
MAC layer algorithm;
actuator networks;
factory automation;
home automation;
power aware fulfilment;
wireless network;
wireless sensor;
12.
High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic
机译:
基于低种族分裂级电荷循环晶体管的高性能CMOS 2输入NAND
作者:
Garcia J.C.
;
Montiel-Nelson J.A.
;
Nooshabadi S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
CMOS integrated circuits;
logic circuits;
CMOS technology;
CMOS two-input NAND;
capacitance 1 pF;
capacitive loading condition;
energy-delay product;
high-output load operation;
low-race split-level charge-recycling pass-transistor logic;
size 65 nm;
charge–recycling;
high capacitive load;
low–energy;
low–voltage;
13.
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures
机译:
一种针对应用领域特定嵌入式体系结构的多目标设计的有效方法论
作者:
Catania V.
;
Nuovo A.
;
Palesi M.
;
Patti D.
;
Morales G.
会议名称:
《》
|
2009年
关键词:
embedded systems;
genetic algorithms;
logic design;
parallel architectures;
application domain-specific embedded architectures;
computer systems;
correlation analysis;
exploration times;
high performance computing;
multiobjective design space exploration;
multiobjective genetic algorithm;
register-level design;
Design Space Exploration;
Multi-Objective Evolutionary Algorithm;
VLIW;
14.
Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links
机译:
用于高速串行链路车载系统的稳健分析的信号完整性和功率完整性方法
作者:
Nagpal R.K.
;
Malik R.
;
Tripathi J.N.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
integrated circuit interconnections;
integrated circuit reliability;
optimisation;
transceivers;
bit error rate requirement;
channel reliability;
decoupling network;
high-bandwidth systems;
high-speed serial links;
integrated system level simulations;
interconnect environment;
on-the-board system;
optimize channel design;
power integrity;
signal integrity;
signal quality inrush droop-drop;
system level robustness analysis;
High Speed Serial Links;
Robust Analysis;
15.
Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models
机译:
通过TLM模型的动态二进制工具进行交易序列跟踪
作者:
da Silva A.
;
Sanchez S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Unified Modeling Language;
data structures;
SystemC;
argument value corruption;
binary transaction saboteurs;
dynamic binary instrumentation;
interchanged transactions;
protocol tracker;
return value corruption;
runtime UML sequence diagrams;
signal communication path;
software routine;
transaction level modeling;
transaction sequence tracking;
Reverse Sequence Diagram;
Transaction Level;
16.
Variation-tolerant Design Using Residue Number System
机译:
使用残数系统的变异容忍设计
作者:
Kouretas I.
;
Paliouras V.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
VLSI;
delays;
residue number systems;
critical paths delay;
delay variation;
residue number system;
variation-tolerant design;
RNS;
SSTA;
residue;
statistical;
variation;
17.
Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems
机译:
可靠联网嵌入式系统设计的时变网络故障模型
作者:
Fummi F.
;
Quaglia D.
;
Stefanni F.
会议名称:
《》
|
2009年
关键词:
delays;
distortion;
embedded systems;
fault simulation;
time-varying networks;
dependable networked embedded systems;
end-to-end delay;
packet losses;
safety-critical tasks;
signal distortion;
time-varying network fault model;
fault model;
networked embedded systems;
simulation;
18.
Title Page iii
机译:
标题页iii
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
19.
Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems
机译:
数字系统中无块级故障模型的调试和诊断
作者:
Ubar R.
;
Kostin S.
;
Raik J.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
cause-effect analysis;
dictionaries;
digital systems;
fault diagnosis;
network analysis;
network topology;
block connectivity;
codewords;
concise block level topological fault dictionary;
fault model free diagnosis;
faulty block;
network;
diagnosability;
diagnostic resolution;
topological fault dictionaries;
20.
Exploration of Slot Allocation for On-Chip TDM Virtual Circuits
机译:
片上TDM虚拟电路的插槽分配探索
作者:
Li Tong
;
Zhonghai Lu
;
Hua Zhang
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
circuit switching;
network-on-chip;
quality of service;
VC configuration flow;
link bandwidth;
maximal virtual circuit bandwidth;
on-chip TDM virtual circuits;
quality-of-service;
search space;
slot allocation;
time division multiplexing;
Virtual Circuit;
21.
Deductive Fault Simulation for Asynchronous Sequential Circuits
机译:
异步时序电路的演绎故障仿真
作者:
Dobai R.
;
Gramatova E.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
asynchronous circuits;
asynchronous sequential logic;
circuit simulation;
fault simulation;
sequential circuits;
SI benchmark circuits;
asynchronous sequential circuits;
deductive fault simulation;
oscillation;
speed-independent asynchronous sequential circuits;
22.
ARROW - A Generic Hardware Fault Injection Tool for NoCs
机译:
ARROW-适用于NoC的通用硬件故障注入工具
作者:
Birner M.
;
Handl T.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
digital integrated circuits;
fault diagnosis;
hardware description languages;
integrated circuit interconnections;
network-on-chip;
Arrow;
NoC;
VHDL;
distributed systems;
fault models;
fault tolerance;
generic hardware fault injection tool;
hardware description language;
interconnect technology;
logical level;
physical faults;
Fault Injection;
23.
Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors
机译:
在多个处理器上映射的实时数据流应用程序的保守动态能源管理
作者:
Molnos A.
;
Goossens K.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
data flow computing;
dynamic scheduling;
multiprocessing systems;
power aware computing;
processor scheduling;
conservative dynamic energy management;
dependency-aware scheduling;
energy reduction;
multiple processors;
real-time dataflow;
share slack;
static slack;
task scheduling;
voltage-frequency scaling;
work slack;
DVFS;
Dataflow;
Multi-processor;
24.
A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC
机译:
EAC的FPGA实现中并行前缀加法器的比较研究
作者:
Feng Liu
;
Forouzandeh F.F.
;
Mohamed O.A.
;
Gang Chen
;
Xiaoyu Song
;
Qingping Tan
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
adders;
field programmable gate arrays;
floating point arithmetic;
microprocessor chips;
trees (mathematics);
128-bit binary floating-point EAC adder;
FPGA;
FPGA EAC adder;
IBM POWER6;
Kogge-Stone tree;
critical path delay;
end-around carry;
logic circuits;
microprocessor;
multiply-add unit;
parallel prefix adders;
parallel prefix trees;
power consumption;
25.
An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs
机译:
网络处理器MPSoC中用于数据包重新排序的高效硬件体系结构
作者:
Traboulsi S.
;
Meitinger M.
;
Ohlendorf R.
;
Herkersdorf A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
field programmable gate arrays;
multiprocessing systems;
network-on-chip;
FPGA;
MPSoC;
buffering techniques;
data packets;
high speed hardware architecture;
multi-processor system-on-chip;
network processors;
packet re-sequencing;
packet reordering;
processing elements;
resource utilization;
Hardware Architecture;
26.
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC
机译:
用于共享内存MPSoC的动态混合缓存一致性协议
作者:
Chtioui H.
;
Ben Atitallah R.
;
Niar S.
;
Dekeyser J.-L.
;
Abid M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
cache storage;
memory protocols;
microprocessor chips;
network-on-chip;
shared memory systems;
CABA simulation platform;
cycle accurate bit accurate;
data coherency problem;
dynamic hybrid cache-coherency protocol implementation;
multiprocessor system-on-chip architecture;
shared-memory MPSoC;
MPSoC;
Shared-memory;
cache coherence;
energy consumption;
performance evaluation;
27.
Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints
机译:
性能和可靠性约束下的异构多处理器综合
作者:
Sugihara M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
embedded systems;
integer programming;
integrated circuit reliability;
linear programming;
microprocessor chips;
multiprocessing systems;
radiation hardening (electronics);
real-time systems;
MILP model;
SEU vulnerability factor;
automatic generation;
chip area minimization;
embedded system;
heterogeneous multiprocessor synthesis;
mixed integer linear programming;
real-time system;
reliability constraints;
single event upsets;
Reliability;
Single Event Upset;
Soft Error;
28.
Composable Resource Sharing Based on Latency-Rate Servers
机译:
基于延迟率服务器的可组合资源共享
作者:
Akesson B.
;
Hansson A.
;
Goossens K.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
SRAM chips;
asynchronous circuits;
buffer circuits;
computer interfaces;
shared memory systems;
SRAM memory;
arbiter;
bounded service time;
buffers;
composable resource sharing;
flow control;
latency-rate servers;
performance analysis;
solution space;
composability;
real-time;
resource sharing;
verification;
29.
A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling
机译:
使用MVCM信令的无危险,延迟不敏感的4相片上链路
作者:
Fattah M.
;
Moghaddam S.A.
;
Mohammadi S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
current-mode circuits;
integrated circuit design;
integrated circuit interconnections;
network-on-chip;
system-on-chip;
NoC design;
SoC design;
dual-rail N-bit data;
dual-rail protocol;
hazard-free communication;
hazard-free delay-insensitive four-phase on-chip link;
interconnection lines;
multiple-valued current-mode signaling;
receiver implementation;
size 130 nm;
transmitter implementation;
two-phase dual-rail asynchronous data bit;
MVCM;
NOC;
SOC;
asynchronous;
current mode signalling;
delay insensitive;
link;
30.
A Priority-Based Budget Scheduler with Conservative Dataflow Model
机译:
具有保守数据流模型的基于优先级的预算计划程序
作者:
Steine M.
;
Bekooij M.
;
Wiggers M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
data flow computing;
multiprocessing systems;
processor scheduling;
task analysis;
time division multiplexing;
TDM scheduler;
conservative dataflow model;
multiprocessor system;
priority-based budget scheduler;
stream processing application;
task graph;
31.
Distributed Collaborative Design of a Mixed-Signal IP Component
机译:
混合信号IP组件的分布式协同设计
作者:
Pawlak A.
;
Penkala P.
;
Fras P.
;
Sakowski W.
;
Grau G.
;
Grzybek S.
;
Stanitzki A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
concurrent engineering;
electronic design automation;
groupware;
industrial property;
integrated circuit design;
mixed analogue-digital integrated circuits;
system-on-chip;
EU FP6 project MAPPER;
SoC;
USB2 OTG PHY IP core design;
collaborative workspace;
distributed collaborative design;
engineering workflow;
enhanced EDA support;
heterogeneous system;
mixed-signal IP component;
mixed-signal USB design;
remote tool invocation;
system-on-chip design;
task pattern design;
visual knowledge modeling;
IP component design;
32.
A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction
机译:
容错的NoC架构,可提高可靠性并减少延迟
作者:
Zonouz A.E.
;
Seyrafi M.
;
Asad A.
;
Soryani M.
;
Fathy M.
;
Berangi R.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
integrated circuit design;
network routing;
network-on-chip;
reliability;
IC designers;
fault tolerant NoC architecture;
faulty switch;
latency;
latency reduction;
reliability improvement;
routing algorithm;
Fault Tolerance;
Network on Chip;
Perfomance Metric;
33.
Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation
机译:
量子量子计算量子位数据移动的可靠性分析
作者:
Boncalo O.
;
Amaricai A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
distributed processing;
quantum computing;
reliability;
trees (mathematics);
EPR distillation protocol;
noise model;
quantum distributed computer;
quantum gate;
qubit data movement;
reliability analysis;
serial purification;
tree based purification protocol;
distributed quantum computation;
simulated fault injection;
34.
Author Index
机译:
作者索引
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
35.
Ad-hoc WSN in Biological Research
机译:
WSN生物研究专案
作者:
Mario P.
;
Fontan F.P.
;
Dominguez M.A.
;
Otero S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
ad hoc networks;
agricultural engineering;
wireless sensor networks;
ad-hoc WSN;
agriculture needs;
biological research;
distributed network;
viticulture applications;
wireless sensors network;
36.
Synthesizing Reversible Circuits for Irreversible Functions
机译:
合成具有不可逆功能的可逆电路
作者:
Miller D.M.
;
Wille R.
;
Dueck G.W.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Boolean functions;
adders;
digital arithmetic;
network synthesis;
Boolean function;
Toffoli gate full adder;
irreversible function;
irreversible specification;
reversible circuit synthesis;
reversible function;
reversible specification;
don't-care assignment;
irreversible functions;
reversible circuits;
synthesis;
37.
A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms
机译:
许多产品术语描述的用于逻辑功能的快速SOP最小化器
作者:
Fiser P.
;
Toman D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Boolean functions;
circuit optimisation;
logic CAD;
logic testing;
minimisation;
trees (mathematics);
basic Boolean operations;
collapsed ISCAS benchmark circuits;
combinational logic functions;
fast SOP minimizer;
standard tabular function representation;
sum-of-product form;
term operation;
ternary tree;
total minimization runtime;
Espresso;
SOP;
logic functions;
two-level minimization;
38.
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
机译:
3D多处理器体系结构的温度和成本感知设计
作者:
Coskun A.K.
;
Kahng A.B.
;
Rosing T.S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
integrated circuit layout;
multiprocessing systems;
optimisation;
system-on-chip;
3D MPSoCs;
3D multiprocessor architectures;
3D stacking;
cost-aware design;
multiprocessor SoC;
power consumption;
size 32 nm;
size 45 nm;
steady state temperature profile;
temperature-aware design;
temperature-aware floorplanning optimization;
3D;
floorplanning;
multiprocessor;
yield;
39.
FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash
机译:
SHA-3候选者的FPGA实现:CubeHash,Grøstl,LANE,Shabal和Spectral Hash
作者:
Baldwin B.
;
Byrne A.
;
Hamilton M.
;
Hanley N.
;
McEvoy R.P.
;
Weibo Pan
;
Marnane W.P.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
cryptographic protocols;
field programmable gate arrays;
file organisation;
CubeHash algorithm;
FPGA;
Grostl algorithm;
Lane algorithm;
Secure Hash Standard;
Shabal algorithm;
Spectral Hash algorithm;
Virtex-5;
Xilinx Spartan-3;
hash functions;
40.
Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture
机译:
对称多处理器体系结构的自适应动态电压和频率缩放算法
作者:
Gligor M.
;
Fournel N.
;
Petrot F.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
multi-threading;
multiprocessing systems;
operating systems (computers);
power aware computing;
system-on-chip;
SMP-SoC;
adaptive dynamic voltage frequency scaling;
nonreal time operating system;
real-life multi-threaded application;
symmetric multiprocessor architecture;
system on chip;
41.
Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques
机译:
开放平台,用于高级软件定义无线电和认知无线电技术的原型制作
作者:
Nussbaum D.
;
Kalfallah K.
;
Knopp R.
;
Moy C.
;
Nafkha A.
;
Leray P.
;
Delorme M.
;
Palicot J.
;
Martin J.
;
Clermidy F.
;
Mercier B.
;
Pacalet R.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
cognitive radio;
protocols;
software radio;
telecommunication computing;
ANR project;
IDROMel;
advanced software defined radio;
cognitive radio techniques;
open platform;
radio frequency front end;
reconfigurable protocol stacks;
NoC;
RF;
Software Defined Radio;
architecture;
base band;
reconfiguration;
42.
Improving Latency of Quantum Circuits by Gate Exchanging
机译:
通过门交换提高量子电路的延迟
作者:
Mohammadzadeh N.
;
Zamani M.S.
;
Sedighi M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
CMOS digital integrated circuits;
integrated circuit design;
optimisation;
CMOS design;
design description;
design flow;
flexible netlist;
gate exchanging;
ion trap technology;
latency;
optimization flow;
quantum circuit;
CAD;
Ion Trap;
Quantum Computing;
43.
Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator
机译:
DVB-S2基带解调器的体系结构和DSP实现
作者:
Savvopoulos P.
;
Papandreou N.
;
Antonakopoulos T.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
demodulators;
digital signal processing chips;
digital video broadcasting;
direct broadcasting by satellite;
radio receivers;
DSP implementation;
DSP software tasks;
DVB-S2 baseband demodulator;
DVB-S2 baseband signal-flow;
DVB-S2 satellite receivers;
demodulator prototyping;
dynamic time-sharing scheduler;
fixed-point implementation;
multidomain signal processing stages;
versatile testbed;
44.
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application
机译:
4G电信开放可重配置平台:概念和应用
作者:
Clermidy F.
;
Lemaire R.
;
Popon X.
;
Ktenas D.
;
Thonnart Y.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
4G mobile communication;
telecommunication;
3GPP-LTE application;
4G telecommunication;
complex data-flow applications;
open platform;
plug-in computing units;
reconfigurable platform;
run-time configuration mechanisms;
static configuration mechanisms;
Network-on-Chip;
Software Defined Radio;
45.
High Availability Fault Tolerant Architectures Implemented into FPGAs
机译:
在FPGA中实现的高可用性容错架构
作者:
Straka M.
;
Kotasek Z.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Markov processes;
fault tolerance;
field programmable gate arrays;
FPGA;
Markov reliability model;
availability parameters;
double modula redundancy system;
fault detection;
fault tolerant architectures;
fault tolerant systems;
field programmable gate array;
on-line checkers;
operating environment;
reliability parameters;
triple modula redundancy system;
TMR;
architecture;
availability;
checker;
duplex;
fault tolerant system;
reliability model;
46.
FPGA Accelerator for RNA Secondary Structure Prediction
机译:
用于RNA二级结构预测的FPGA加速器
作者:
Diaz-Perez A.
;
Garcia-Martinez M.A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
biology computing;
field programmable gate arrays;
hardware description languages;
molecular biophysics;
parallel architectures;
pipeline processing;
FPGA accelerator;
ModelSim 6.1e;
O(n) time complexity solution;
RNA secondary structure prediction;
VHDL description;
Xilinx FPGAs;
circuit verification;
classic O(nsup3/sup) algorithm;
computational resources;
package ISE8.1i;
parallel computing;
parallel design;
pipeline design;
ribonucleic acid molecules;
software implementations;
FPGA;
RNA-problem;
accelerator ci;
47.
Pulse Generation for On-chip Data Transmission
机译:
脉冲生成,用于片上数据传输
作者:
Hollis S.J.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
RLC circuits;
asynchronous circuits;
inductance;
network-on-chip;
pulse generators;
NoC;
RC model;
RLC model;
energy efficiency;
full pulse-based asynchronous network-on-chip;
on-chip data transmission;
pulse generator;
pulse-based data transmission;
signal integrity;
size 1.25 mm to 3 mm;
Interconnect;
energy-efficiency;
low-swing;
on-chip communication;
pulse-signalling;
repeaters;
48.
Compilation Technique for Loop Overhead Minimization
机译:
循环开销最小化的编译技术
作者:
Kroupis N.
;
Raghavan P.
;
Jayapala M.
;
Catthoor F.
;
Soudris D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
embedded systems;
optimising compilers;
program control structures;
compilation technique;
division operations;
handheld embedded systems;
highly data-dominated applications;
induction variable analysis;
loop control instruction execution;
loop controller architectures;
loop overhead minimization;
multimedia domain;
nested-loop execution time;
real-time constraints;
wireless domain;
49.
Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation
机译:
并行余数估计的Golschmidt算法的可变延迟舍入
作者:
Piso D.
;
Braguera J.D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
algorithm theory;
Golschmidt algorithm;
functional iteration algorithm;
parallel remainder estimation;
remainder calculation;
variable latency rounding algorithm;
50.
Low Power Encoding in NoCs Based on Coupling Transition Avoidance
机译:
基于耦合转移避免的NoC中的低功耗编码
作者:
Taassori M.
;
Hessabi S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
crosstalk;
integrated circuit interconnections;
network-on-chip;
NoCs;
adjacent links;
adjacent wires;
chip interconnects;
coupling capacitances;
coupling transition avoidance;
crosstalk noise;
high-speed design;
low power encoding;
network-on-chip architecture;
on-chip interconnects;
power consumption;
propagation delay;
signal integrity;
ultradeep-submicron technology;
Coupling capacitance;
Network on Chip;
51.
A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes
机译:
WSN节点中非功能性方面的编译时和运行时管理框架
作者:
Brandolese C.
;
Fornaciari W.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
ad hoc networks;
power consumption;
telecommunication network reliability;
telecommunication security;
time management;
wireless sensor networks;
WSN nodes;
ad-hoc networks;
compile-time management;
energy consumption;
network lifetime;
network reliability;
network security;
optimization trade-off;
realistic complex wireless sensor networks;
run-time management;
Non-functional aspects;
Power management;
52.
GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids
机译:
GridRT:使用均匀网格进行光线追踪的大规模并行架构
作者:
Nery A.S.
;
Nedjah N.
;
Frana F.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
floating point arithmetic;
grid computing;
parallel architectures;
ray tracing;
rendering (computer graphics);
spatial data structures;
GridRT;
Xilinx;
floating point operator IP core;
massively parallel architecture;
reflections;
regular grids;
rendering;
shadows;
spatial data structure;
three-dimensional scenes;
uniform grids;
Architecture;
Computer Graphics;
FPGA;
Uniform Grid;
53.
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables
机译:
使用最少数量的复合变量表示不完整指定的索引生成函数
作者:
Sasao T.
;
Nakamura T.
;
Matsuura M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
digital arithmetic;
heuristic programming;
logic gates;
programmable circuits;
table lookup;
EXOR gates;
EXORing;
bi-compound variables;
compound variables;
heuristic method;
incompletely specified index generation functions;
information gains;
lookup table;
multiplexers;
original variables;
primitive variables;
programmable hash circuit;
random functions;
registers;
EXOR gate;
linear transformation;
logic minimization;
patterm matching;
54.
Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis
机译:
优化的可重新配置RTL组件,可在高级综合过程中提高性能
作者:
Economakos G.
;
Xydis S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
high level synthesis;
optimisation;
reconfigurable architectures;
coarse grain reconfigurable components;
gate-level synthesis methodology;
high-level synthesis;
multiplier;
optimized reconfigurable RTL components;
reconfigurable computing;
register transfer level;
register-transfer level components;
run time reconfiguration;
55.
The Parallel Sieve Method for a Virus Scanning Engine
机译:
病毒扫描引擎的并行筛选方法
作者:
Nakahara H.
;
Sasao T.
;
Matsuura M.
;
Kawamura Y.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
DRAM chips;
SRAM chips;
computer viruses;
field programmable gate arrays;
SDRAM;
Stratix III FPGA;
TCAM-based method;
finite-input memory machine;
hardware filter;
intrusion detection system;
off-chip SRAM;
parallel sieve method;
two-stage matching;
virus scanning engine;
FPGA;
Network;
Reconfigurable Architecture;
Virus Scanning;
56.
Reliable Railway Station System Based on Regular Structure Implemented in FPGA
机译:
用FPGA实现的基于规则结构的可靠火车站系统
作者:
Borecky J.
;
Kubalik P.
;
Kubatova H.
会议名称:
《》
|
2009年
关键词:
field programmable gate arrays;
railway safety;
railways;
reliability;
FPGA;
Moore type;
basic blocks;
finite state machine;
regular structure;
reliable railway station system;
self-checking circuit;
universal interface;
Fault Tolerant design;
Railway Station;
SEU;
Secure Device;
57.
Internet-Router Buffered Crossbars Based on Networks on Chip
机译:
基于片上网络的Internet路由器缓冲交叉开关
作者:
Goossens K.
;
Mhamdi L.
;
Senin I.V.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Internet;
buffer circuits;
computer interfaces;
multiprocessor interconnection networks;
network routing;
network-on-chip;
packet switching;
resource allocation;
CMOS technology;
FIFO-queued line cards;
Internet router;
NOC inter-router wires;
arbitration;
input-output port pairs;
internal buffers;
load balancing;
multi-hop crossbar fabric;
multi-hop network-on-chip;
packet switches;
path diversity;
router buffers;
scalability;
58.
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip
机译:
元模型辅助优化的片上多处理器系统设计空间探索
作者:
Mariani G.
;
Palermo G.
;
Silvano C.
;
Zaccaria V.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Pareto optimisation;
approximation theory;
evolutionary computation;
multiprocessing systems;
neural nets;
statistical analysis;
system-on-chip;
ANN approximations;
MOO problem;
NSGA-II modified;
Pareto front identification;
artificial neural network;
design space exploration;
evolution control strategy;
meta-model assisted optimization;
multiobjective optimization;
multiprocessor system-on-chip;
platform-based synthesis technique;
statistical methods;
Multi-Objective Optimization;
Multi-Processor System on Chip;
59.
High Performance Image Processing on a Massively Parallel Processor Array
机译:
大规模并行处理器阵列上的高性能图像处理
作者:
Osorio R.R.
;
Diaz-Resco C.
;
Bruguera J.D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
field programmable gate arrays;
image coding;
image processing;
program processors;
Ambric massively parallel processor array;
FPGAs;
hardware design;
jpeg;
manycore;
mppa;
multicore;
stream processing;
60.
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
机译:
高清晰度视频的可重构帧插值硬件架构
作者:
Tasdizen O.
;
Hamzaoglu I.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
field programmable gate arrays;
hardware description languages;
interpolation;
reconfigurable architectures;
Macroblock;
VHDL;
Xilinx XC3SD1800A-4 FPGA;
adaptive selection;
frame interpolation algorithms;
frame rate up-conversion;
frequency 101 MHz;
high definition video;
reconfigurable hardware architecture;
FPGA;
Frame Interpolation;
Hardware Implementation;
61.
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
机译:
一种基于一位变换的运动估计的高性能硬件架构
作者:
Akin A.
;
Dogan Y.
;
Hamzaoglu I.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
data compression;
field programmable gate arrays;
hardware description languages;
motion estimation;
systolic arrays;
video coding;
Verilog HDL;
Xilinx XC2VP30-7 FPGA;
computational complexity;
data reuse scheme;
high definition frames;
high performance systolic hardware architecture;
memory organization;
on-chip memory;
one bit transform;
real-time video compression;
real-time video processing;
62.
A Concept for Logic Self Repair
机译:
逻辑自我修复的概念
作者:
Koal T.
;
Scheit D.
;
Vierhaus H.T.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
built-in self test;
circuit testing;
logic circuits;
associated overhead;
built-in self repair;
logic BISR;
logic self repair;
memory blocks;
permanent faults;
regular structures;
transient faults;
63.
Title Page i
机译:
标题页
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
digital radio;
fault tolerance;
flexible electronics;
hardware-software codesign;
logic circuits;
multiprocessing systems;
network synthesis;
optimisation;
system-on-chip;
wireless sensor networks;
HW-SW embedded systems;
arithmetic circuit synthesis;
circuit design;
digital system design;
digital system testing;
embedded-digital system applications;
flexible digital radio;
logic synthesis;
multiprocessor;
programmable-re-configurable architectures;
system synthesis;
system-level energy optimization;
systems-on-a-chi;
64.
Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation
机译:
用于硬件/软件代码生成的系统应用程序和硬件体系结构的抽象描述
作者:
El Mrabti A.
;
Sheibanyrad H.
;
Rousseau F.
;
Petrot F.
;
Lemaire R.
;
Martin J.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
abstract data types;
formal specification;
hardware-software codesign;
program compilers;
abstract description;
abstract modeling;
code generation flow;
complex 4G telecommunication application;
computation requirement;
design process;
hardware architecture;
hardware-software code generation;
meta-mapping;
system application;
65.
An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm
机译:
基于FPGA的仅相位相关算法的指纹匹配嵌入式系统
作者:
Danese G.
;
Giachero M.
;
Leporati F.
;
Matrone G.
;
Nazzicari N.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
correlation methods;
embedded systems;
field programmable gate arrays;
fingerprint identification;
image matching;
image processing equipment;
AFIS;
COTS components;
FPGA;
automatic fingerprint identification systems;
biometric identification system;
computationally demanding core;
embedded system;
fingerprint matching;
matching algorithm;
phase-only spatial correlation;
Applications Specific Processors;
66.
Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems
机译:
无线通信系统中FFT / FIR单元的重新配置级别分析
作者:
Ojail M.
;
David R.
;
Chevobbe S.
;
Demigny D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
FIR filters;
fast Fourier transforms;
radiocommunication;
telecommunication standards;
3G;
DVB-H;
FFT;
IEEE 802.11g;
UMTS;
WLAN;
finite impulse response filters;
multiple radio access techniques;
multiple telecommunications standards;
reconfiguration level analysis;
wireless telecommunication systems;
FIR;
Reconfigurable architectures;
wireless telecommunication;
67.
Power Management Aware Low Leakage Behavioural Synthesis
机译:
电源管理意识低泄漏行为综合
作者:
Rosinger S.
;
Schroder K.
;
Nebel W.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
high level synthesis;
integer programming;
linear programming;
low-power electronics;
ILP-based scheduling;
allocation optimization;
binding approach;
low leakage behavioural synthesis;
operation clustering;
operation scheduling;
power management;
behavioural synthesis;
leakage optimization;
power gating;
68.
The Case for a Balanced Decomposition Process
机译:
平衡分解过程的理由
作者:
Fiser P.
;
Schmidt J.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
network synthesis;
parity;
LEKU examples;
balanced decomposition process;
logic synthesis;
parity examples;
synthesis tools;
LEKU;
bi-decomposition;
decomposition;
example;
69.
Design of a Highly Dependable Beamforming Chip
机译:
高可靠性波束形成芯片的设计
作者:
Xiao Zhang
;
Kerkhoff H.G.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
CMOS digital integrated circuits;
digital signal processing chips;
integrated circuit reliability;
reconfigurable architectures;
system-on-chip;
CMOS process;
IEC standard 62347;
SoC complexity;
dependability graphs;
design-for-dependability hardware;
design-for-dependability software;
functional dependability analysis;
highly dependable beamforming chip;
reconfigurable Xentium tile processors;
run-time mapping reconfiguration software;
size 32 nm;
SoC;
beamforming;
dependability;
design-for-dependability;
reconfig;
70.
Iterative Algorithm for Compound Instruction Selection with Register Coalescing
机译:
寄存器合并的复合指令选择迭代算法
作者:
Minwook Ahn
;
Youn J.M.
;
Youngkyu Choi
;
Doosan Cho
;
Yunheung Paek
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
embedded systems;
encoding;
instruction sets;
iterative methods;
program compilers;
ALU encoding;
compiler;
compound instruction selection;
detrimental impact;
embedded processors;
instruction selection phase;
instruction word;
iterative algorithm;
iterative code generation algorithm;
memory operation encoding;
register coalescing;
compound instruction;
nullified compound instructions;
71.
An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions
机译:
ROB的高效,低复杂度替代方案,可无序撤消指令
作者:
Petit S.
;
Ubal R.
;
Sahuquillo J.
;
Lopez P.
;
Duato J.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
buffer circuits;
microprocessor chips;
ROB-based microprocessor;
checkpoint-free out-of-order commit architecture;
out-of-order instruction retirement;
register reclamation;
register reclamation mechanism;
superscalar reorder buffer processors;
validation buffer;
72.
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism
机译:
具有动态调度机制的同时多线程VLIW DSP架构
作者:
Zheng Shen
;
Hu He
;
Yihe Sun
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
digital signal processing chips;
multi-threading;
parallel architectures;
NUAL VLIW DSP architecture;
cache miss latency;
computing resource underutilization;
digital signal processing;
digital signal processor;
dynamic dispatch mechanism;
execution-packet;
instruction-level parallelism;
multithreading VLIW DSP architecture;
nonunit assumed latency;
thread-level parallelism;
very-long instruction word architectures;
DSP;
Dynamic dispatch;
SMT;
VLIW;
73.
CPLD-oriented Synthesis of Finite State Machines
机译:
面向CPLD的有限状态机综合
作者:
Czerwinski R.
;
Kania D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
finite state machines;
programmable logic arrays;
state assignment;
CPLD;
FSM;
PAL-oriented multilevel optimization;
finite state machine synthesis;
state assignment method;
logic optimization;
logic synthesis;
74.
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
机译:
异步处理器的可合成准延迟不敏感结果转发单元
作者:
Tarazona L.A.
;
Edwards D.A.
;
Plana L.A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
asynchronous circuits;
microprocessor chips;
network synthesis;
asynchronous processor;
automatic synthesis;
design space exploration;
quasidelay insensitive result forwarding unit;
syntax-directed synthesis;
technology mapping transparency;
asynchronous design;
quasi-delay insensitive;
result forwarding;
75.
Copyright Page
机译:
版权页
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
76.
Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks
机译:
能量受限片上网络的每核DVFS的体系结构探索
作者:
Yin A.W.
;
Liang Guang
;
Nigussie E.
;
Liljeberg P.
;
Isoaho J.
;
Tenhunen H.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
integrated circuit interconnections;
network-on-chip;
power supply circuits;
NoC;
architectural exploration;
average flit energy consumption;
dynamic voltage and frequency scaling;
energy-constrained on-chip networks;
high-level simulation;
multiple voltage supply networks;
on-chip interconnection;
per-core DVFS;
power selecting transistors;
traffic patterns;
77.
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip
机译:
虫孔交换片上网络中的低功耗数据编码
作者:
Palesi M.
;
Fazzino F.
;
Ascia G.
;
Catania V.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
encoding;
low-power electronics;
network routing;
network-on-chip;
NoC;
communication protocols;
communication system;
coupling switching activity;
data encoding;
endto-end data encoding;
energy consumption;
inter-routers links;
on-chip communication infrastructure;
power dissipation;
power ratio;
representative data streams;
self switching activity;
wormhole switching;
Coupling capacitance;
Low power;
Network on Chip;
Power analysis;
78.
Roster Page
机译:
名册页
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
79.
Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms
机译:
基于NoC的异构MPSoC平台的映射算法
作者:
Singh A.K.
;
Wu Jigang
;
Prakash A.
;
Srikanthan T.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
multiprocessing systems;
network-on-chip;
reconfigurable architectures;
system-on-chip;
NoC-based heterogeneous MPSoC platforms;
communication overhead minimization;
hardware tasks;
mapping algorithms;
multiprocessor system-on-chip;
network-on-chip congestion bottlenecks;
reconfigurable processing node;
run-time mapping heuristics;
Multiprocessor System-on-Chip (MPSoC) Design;
Network-on-Chip (NoC);
Run-time mapping;
80.
Performance-Effective Compaction of Standard-Cell Libraries for Digital Design
机译:
用于数字设计的标准单元库的性能有效压缩
作者:
Ricci A.
;
De Munari I.
;
Ciampolini P.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
VLSI;
digital integrated circuits;
digital libraries;
electronic design automation;
integrated circuit design;
logic design;
logic gates;
EDA;
benchmark circuits;
circuit synthesis;
digital design;
general-purpose circuit design;
library maintenance;
library-reduction strategy;
performance-effective compaction;
standard-cell library;
two-input AND gate design;
algorithm;
complexity reduction;
81.
High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output
机译:
用于0.5V输入和1V输出的高性能自举CMOS双电源电平转换器
作者:
Garcia-Montesdeoca J.C.
;
Montiel-Nelson J.A.
;
Nooshabadi S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
CMOS integrated circuits;
MOSFET;
bootstrap circuits;
capacitance;
capacitors;
integrated circuit design;
CMOS dual supply level shifter;
bootstrap capacitor;
capacitance 2 pF;
capacitive loading;
energy-delay product;
input capacitance;
output pull-down NMOS transistor;
output pull-up PMOS transistor;
ts-level shifter;
vj-level shifter;
voltage difference;
high capacitive load;
level–shifter;
low–energy;
low–voltage;
82.
An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication
机译:
FPGA内部的片上网络,用于运行时可重新配置的低延迟网格通信
作者:
Strunk J.
;
Volkmer T.
;
Rehm W.
;
Schick H.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
field programmable gate arrays;
grid computing;
network-on-chip;
dedicated silicon network;
host coupled FPGA accelerator;
intercommunicating offload compute kernel;
on chip communication network;
partially reconfigurable FPGA;
run time reconfigurable low latency grid communication;
run time reconfigurable module;
FPGA;
Network on Chip;
NoC;
dynamic and partial reconfiguration;
run-time reconfiguration;
83.
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
机译:
S-NUCA CMP运行科学工作量的行为评估
作者:
Foglia P.
;
Panicucci F.
;
Prete C.A.
;
Solinas M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
cache storage;
message passing;
multiprocessing systems;
network-on-chip;
MES1 topology;
MOESI topology;
NOC bandwidth utilization;
NUCA caches;
NoC;
S-NUCA CMPs;
access distribution;
chip multiprocessors;
coherence protocol;
communication infrastructure;
data mapping;
fixed topology;
nonuniform cache access architecture;
private LI caches;
processor topology;
scientific workload;
shared L2 cache;
static NUCA;
NUCA;
cache;
latency;
mapping;
topology;
wire-delay;
84.
Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation
机译:
使用可变延迟商生成提高除法融合运算的性能
作者:
Amaricai A.
;
Boncalo O.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
floating point arithmetic;
addition;
divide-add fused operation;
floating point units;
latency;
quotient bits;
subtraction;
variable latency quotient generation;
digital arithmetic;
divide-add fused;
division;
85.
An Effective Replacement Strategy of Cache Memory for an SMT Processor
机译:
SMT处理器缓存的有效替换策略
作者:
Ogasawara Y.
;
Nakajo H.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
cache storage;
microprocessor chips;
multi-threading;
ALU;
SMT processor;
cache memory;
effective replacement strategy;
pseudo LRU strategy;
simultaneous multithreading processor;
Multithreaded Processor;
Replacement Strategy;
86.
Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs
机译:
FPGA上具有部分透视的双精度Gauss-Jordan算法
作者:
Duarte R.
;
Neto H.
;
Vestias M.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
embedded systems;
field programmable gate arrays;
floating point arithmetic;
pipeline arithmetic;
reconfigurable architectures;
FPGA;
Gauss-Jordan elimination;
Matlab;
Scilab;
Virtex-5;
arithmetic units;
double precision floating point representation;
double-precision Gauss-Jordan algorithm;
embedded processing elements;
matrix inversions;
partial pivoting;
pipeline;
reconfigurable digital system;
87.
Storage Architecture for an On-chip Multi-core Processor
机译:
片上多核处理器的存储架构
作者:
Mengxiao Liu
;
Weixing Ji
;
Jiaxin Li
;
Xing Pu
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
cache storage;
memory architecture;
object-oriented methods;
parallel architectures;
parallel memories;
shared memory systems;
hierarchical shared memory system architecture;
link structured object organization;
memory parallel access efficiency;
new objects management model;
object-oriented systems;
on-chip multi-core processor;
partially-inclusive cache mapping;
storage architecture;
88.
Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors
机译:
在测试平台生成中使用整数线性规划来评估通信处理器
作者:
Senn E.
;
Monnereau D.
;
Rossi A.
;
Julien N.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
benchmark testing;
integer programming;
linear programming;
microprocessor chips;
multiprocessing systems;
performance evaluation;
Intel processor;
MediaBench application suite;
communication processors;
enumerative method;
integer linear programming;
micro-architecture independent characteristics;
synthetic test benches;
test-bench generation;
Benchmark Synthesis;
Instruction Mix;
Processor Evaluation;
89.
Combined SD-RNS Constant Multiplication
机译:
组合SD-RNS常数乘法
作者:
Vassalos E.
;
Bakalis D.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
multiplying circuits;
residue number systems;
combined SD-RNS constant multiplication;
constant operand recoding;
residue number system;
signed-digit representation;
2^n;
2^n+1} arithmetic;
CSD representation;
constant multiplication;
modulo {2^n-1;
signed-digit number system;
90.
Instruction Precomputation for Fault Detection
机译:
用于故障检测的指令预计算
作者:
Borodin D.
;
Juurlink B.H.H.
;
Kaxiras S.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
error detection;
fault diagnosis;
fault tolerant computing;
duplication method;
fault coverage;
fault detection;
hardware faults;
instruction memoization;
instruction precomputation technique;
reliability;
fault tolerance;
instruction precomputation;
91.
Logic Minimization and Testability of 2SPP-P-Circuits
机译:
2SPP-P电路的逻辑最小化和可测试性
作者:
Bernasconi A.
;
Ciriani V.
;
Trucco G.
;
Villa T.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Boolean functions;
circuit testing;
information theory;
logic gates;
2SPP-P-circuit;
AND gate;
Boolean function decomposition;
OR gate;
Shannon cofactoring;
XOR gate;
delay;
logic decomposition;
logic minimization;
minimum area penalty;
projected subfunctions;
stuck-at-fault model;
switching activity;
testability;
2-SPP circuit;
logic synthesis;
multi-level synthesis;
92.
Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds
机译:
盐度梯度太阳能池热性能的远程监测
作者:
Simic M.N.
;
Singh R.
;
Doukas L.
;
Akbarzadeh A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
data acquisition;
solar absorber-convertors;
solar ponds;
telemetry;
wireless sensor networks;
data acquisition system;
green energy production control;
remote monitoring;
salinity gradient solar pond;
sensor network;
solar energy collector efficiency;
water turbidity;
Remote Data;
Salinity Gradient;
Solar Pond;
93.
Robustness Check for Multiple Faults Using Formal Techniques
机译:
使用形式化技术对多个故障进行鲁棒性检查
作者:
Frehse S.
;
Fey G.
;
Suflow A.
;
Drechsler R.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Boolean functions;
fault diagnosis;
logic testing;
radiation hardening (electronics);
sequential circuits;
Boolean satisfiability;
VLSI circuits;
fault model;
formal verification;
multiple event upset;
multiple faults;
multiple soft errors;
sequential circuit model;
multiple event upsets;
robustness;
soft errors;
94.
An FPGA-Based Embedded System for a Sailing Robot
机译:
基于FPGA的航行机器人嵌入式系统
作者:
Alves J.C.
;
Cruz N.A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Linux;
boats;
embedded systems;
field programmable gate arrays;
robot programming;
FPGA-based embedded system;
Microblaze soft processor;
WiFi link;
XILINX FPGA;
actuators;
boat control system;
communication devices;
computational load;
computing system;
embedded hardware/software implementation;
graphic interactive application;
hardware domain;
integrated single-chip computing system;
interfacing modules;
remote configuration;
remote monitoring;
remote operation;
sensors;
small scale unmanned autonomous sailing boat;
95.
Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC
机译:
CMOS 0.06mm ^ 2 150MS / s 8位ADC的校准方法
作者:
Petrellis N.
;
Birbas M.
;
Kikidis J.
;
Birbas A.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
CMOS digital integrated circuits;
analogue-digital conversion;
calibration;
dividing circuits;
trees (mathematics);
CMOS technology;
amplification;
analog-to-digital converter;
asynchronous 8-bit ADC;
binary tree structure;
current mode 8-bit ADC;
digital calibration method;
integer division circuits;
offset correction;
power 34 mW;
root divider;
voltage supply;
Analog Digital Conversion;
Integer Division;
96.
Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology
机译:
Ofdm-802.11p系统的递归系统卷积代码仿真和使用ESL方法的FPGA实现
作者:
Kiokes G.
;
Economakos G.
;
Amditis A.
;
Uzunoglu N.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
IEEE standards;
OFDM modulation;
ad hoc networks;
convolutional codes;
field programmable gate arrays;
performance evaluation;
recursive functions;
road safety;
road traffic;
telecommunication channels;
traffic engineering computing;
turbo codes;
ESL methodology;
IEEE 802.11p;
OFDM system;
ad-hoc communication;
communication channels;
electronic system level methodology;
field programmable gate array;
recursive systematic convolutional code simulation;
road transport;
turbo coding;
vehicle safety;
vehicular ad-hoc net;
97.
Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder
机译:
基于NAND的单电子2-4解码器的设计,仿真和性能评估
作者:
Tsiolakis T.
;
Konofaos N.
;
Alexiou G.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
Monte Carlo methods;
circuit simulation;
decoding;
logic gates;
network synthesis;
single electron devices;
Monte-Carlo based tool;
NAND gates;
free energy history diagrams;
performance evaluation;
single-electron 2-4 decoder;
stability plot;
Decoder;
NAND;
Single Electron;
98.
A MPSoC Prototyping Platform for Flexible Radio Applications
机译:
用于灵活无线电应用的MPSoC原型开发平台
作者:
Hedde D.
;
Horrein P.-H.
;
Petrot F.
;
Rolland R.
;
Rousseau F.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
field programmable gate arrays;
multiprocessing systems;
software prototyping;
software radio;
system-on-chip;
MPSoC;
field programmable gate array;
flexible radio;
multi-processor system-on-chip;
prototyping platform;
hardware design;
prototyping;
reconfigurable design;
wireless communications;
99.
Run-Time Reconfigurable Array Using Magnetic RAM
机译:
使用电磁RAM的运行时可重配置阵列
作者:
Silva V.
;
Oliveira L.B.
;
Fernandes J.R.
;
Vestias M.P.
;
Neto H.C.
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
MRAM devices;
flash memories;
SRAM;
coarse-grained magnetic RAM;
data-oriented algorithms;
fine-grained architectures;
flash memory;
magnetic random-access memories;
one-dimensional array;
operation-level parallelism;
programmable ALU;
run-time reconfigurable array architecture;
word length 4 bit;
MRAM;
programmable fabrics;
reconfigurable array;
100.
Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip
机译:
片上网络上基于流水线的高吞吐量低能耗映射
作者:
Ming-Yan Yu
;
Ming Li
;
Jun-Jie Song
;
Fang-Fa Fu
;
Yu-Xin Bai
会议名称:
《Digital System Design, Architectures, Methods and Tools, 2009. DSD '09》
|
2009年
关键词:
multiprocessing systems;
network-on-chip;
pipeline processing;
scheduling;
task analysis;
MPSoC;
NoC architecture;
SystemC;
communication scheduling;
cycle-accurate simulator;
energy-aware mapping algorithm;
high throughput low energy mapping;
pipelining;
streaming;
task allocation;
task scheduling;
Mapping;
Pipeline;
energy-aware;
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