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Automation and Test in Europe Conference and Exhibition
Automation and Test in Europe Conference and Exhibition
召开年:
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1.
Fast hardware-software co-simulation using VHDL models
机译:
使用VHDL型号快速硬件软件共模
作者:
Tabbara B.
;
Sgroi M.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
2.
Iterative improvement based multi-way netlist partitioning for FPGAs
机译:
基于FPGA的迭代改进的多路网表分区
作者:
Krupnova H.
;
Saucier G.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
3.
Design for testability method for CML digital circuits
机译:
CML数字电路可测试方法设计
作者:
Antaki B.
;
Savaria Y.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
4.
On the design of self-checking functional units based on Shannon circuits
机译:
基于Shannon电路的自检功能单位设计
作者:
Favilli M.
;
Metra C.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
5.
MOCSYN: multiobjective core-based single-chip system synthesis
机译:
MOCSYN:基于多目标核心单芯片系统的合成
作者:
Dick R.P.
;
Jha N.K.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
6.
Hierarchical constraint transformation using directed interval search for analog system synthesis
机译:
使用定向间隔搜索模拟系统合成的分层约束转换
作者:
Dhanwada N.R.
;
Nunez-Aldana A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
7.
The design space layer: supporting early design space exploration for core-based designs
机译:
设计空间层:支持基于核心设计的早期设计空间探索
作者:
Peixoto H.P.
;
Jacome M.F.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
8.
Opportunities and challenges in building silicon products in 65nm and beyond
机译:
在65nm及以后建造硅产品的机遇和挑战
作者:
Spirakis G.S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit design;
integrated circuit modelling;
design for testability;
design for manufacture;
elemental semiconductors;
silicon;
silicon products;
integrated semiconductor products;
silicon technology;
Moore law;
technology scaling;
heterogeneous technologies;
RF;
MEMS;
design technology;
functional validation;
timing validation;
design for test;
65 nm;
Si;
9.
Package design for high performance ICs
机译:
高性能IC的包装设计
作者:
Dandia S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit design;
integrated circuit packaging;
lead bonding;
flip-chip devices;
product development;
package design;
integrated circuits;
product development;
co-design process;
wire bond packages;
flip chip design process;
10.
Opportunities and challenges in building silicon products in 65nm and beyond
机译:
在65nm及以后建造硅产品的机遇和挑战
作者:
Spirakis G.S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit design;
integrated circuit modelling;
design for testability;
design for manufacture;
elemental semiconductors;
silicon;
silicon products;
integrated semiconductor products;
silicon technology;
Moore law;
technology scaling;
heterogeneous technologies;
RF;
MEMS;
design technology;
functional validation;
timing validation;
design for test;
65 nm;
Si;
11.
Package design for high performance ICs
机译:
高性能IC的包装设计
作者:
Dandia S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit design;
integrated circuit packaging;
lead bonding;
flip-chip devices;
product development;
package design;
integrated circuits;
product development;
co-design process;
wire bond packages;
flip chip design process;
12.
A SystemC-based verification methodology for complex wireless software IP
机译:
用于复杂无线软件IP的基于系统的验证方法
作者:
Post G.
;
Venkataraghavan P.K.
;
Ray T.
;
Seetharaman D.R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
hardware-software codesign;
3G mobile communication;
integrated circuit modelling;
formal verification;
software architecture;
embedded systems;
SystemC-based verification methodology;
wireless software IP;
intellectual property;
complex lower-level software;
system platform;
embedded software;
lab prototype equipment;
hardware IP;
software-centric hardware-software implementation;
3G WCDMA modem;
software design;
subsystem architecture;
3G hardware;
protocol stack;
instruction set simulator;
high data rate service;
hardware architecture;
3G software;
13.
Stimuli generation with late binding of values
机译:
刺激生成具有后期绑定的值
作者:
Ziv A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
automatic test pattern generation;
digital simulation;
circuit simulation;
formal verification;
hardware-software codesign;
stimuli generation;
late value binding;
test-cases generation;
functional verification;
test generators;
simulation time;
hardware design cycle;
dynamic generation;
14.
A SystemC-based verification methodology for complex wireless software IP
机译:
用于复杂无线软件IP的基于系统的验证方法
作者:
Post G.
;
Venkataraghavan P.K.
;
Ray T.
;
Seetharaman D.R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
hardware-software codesign;
3G mobile communication;
integrated circuit modelling;
formal verification;
software architecture;
embedded systems;
SystemC-based verification methodology;
wireless software IP;
intellectual property;
complex lower-level software;
system platform;
embedded software;
lab prototype equipment;
hardware IP;
software-centric hardware-software implementation;
3G WCDMA modem;
software design;
subsystem architecture;
3G hardware;
protocol stack;
instruction set simulator;
high data rate service;
hardware architecture;
3G software;
15.
Stimuli generation with late binding of values
机译:
刺激生成具有后期绑定的值
作者:
Ziv A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
automatic test pattern generation;
digital simulation;
circuit simulation;
formal verification;
hardware-software codesign;
stimuli generation;
late value binding;
test-cases generation;
functional verification;
test generators;
simulation time;
hardware design cycle;
dynamic generation;
16.
C-based synthesis experiences with a behavior synthesizer, 'Cyber'
机译:
基于C的合成经验与行为合成器,“Cyber”
作者:
Wakabayashi K.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
17.
JAVA VHDL-AMS, ADA Or C For System Level Specifications?
机译:
Java VHDL-AMS,ADA或C用于系统级规格?
作者:
Nebel W.
;
Moser E.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
18.
Multi-language system design
机译:
多语言系统设计
作者:
Jerraya A.
;
Ernst R.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
19.
Index of Authors
机译:
作者指数
作者:
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
20.
Illegal state space identification for sequential circuit test generation
机译:
序贯电路测试生成的非法状态空间识别
作者:
Konijnenburg M.
;
van der Linden J.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
21.
Data type analysis for hardware synthesis from object-oriented models
机译:
从面向对象模型的硬件合成数据类型分析
作者:
Radetzki M.
;
Stammermann A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
22.
Chip-level verification for parasitic coupling effects in deep-submicron digital designs
机译:
深度亚微米数字设计中寄生耦合效应的芯片级验证
作者:
Lun Ye
;
Foong-Charn Chang
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
23.
Minimal length diagnostic tests for analog circuits using test history
机译:
使用测试历史的模拟电路的最小长度诊断测试
作者:
Gomes A.V.
;
Chatterjee A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
24.
Symmetric transparent BIST for RAMs
机译:
用于公羊的对称透明BIST
作者:
Yarmolik V.N.
;
Hellebrand S.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
25.
Post-placement residual-overlap removal with minimal movement
机译:
放置后剩余重叠拆除最小运动
作者:
Nag S.
;
Chaudhary K.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
26.
Automatic verification of scheduling results in high-level synthesis
机译:
自动验证调度导致高级合成
作者:
Eveking H.
;
Hinrichsen H.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
27.
An analog performance estimator for improving the effectiveness of CMOS analog systems circuit synthesis
机译:
一种提高CMOS模拟系统电路合成效能的模拟性能估计
作者:
Nunez-Aldana A.
;
Vemuri R.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
28.
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
机译:
表达式:通过编译器/模拟器retaritability进行架构探索的语言
作者:
Halambi A.
;
Grun P.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
29.
Channel-based behavioral test synthesis for improved module reachability
机译:
基于通道的行为测试合成,可改进模块可达性
作者:
Makris Y.
;
Orailoglu A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
30.
A methodology and design environment for DSP ASIC fixed point refinement
机译:
DSP AsiC定点改进的方法与设计环境
作者:
Cmar R.
;
Rijnders L.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
31.
Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams
机译:
使用决定判定图的可解释大型模拟电路的象征性小信号特征
作者:
Xiang-Dong Tan
;
Shi C.-J.R.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
32.
Combining software synthesis and hardware/software interface generation to meet hard real-time constraints
机译:
结合软件综合和硬件/软件界面生成,以满足硬实时约束
作者:
Vercauteren S.
;
van der Steen J.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
33.
Codex-dp: co-design of communicating systems using dynamic programming
机译:
Codex-DP:使用动态编程的通信系统共同设计
作者:
Jui-Ming Chang
;
Pedram M.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
34.
Exploiting state equivalence on the fly while applying code motion and speculation
机译:
在应用代码运动和猜测的同时,在飞行中利用状态等价
作者:
dos Santos L.C.V.
;
Jess J.A.G.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
35.
Exploring the combination of I/sub DDQ/ and i/sub DDt/ testing: energy testing
机译:
探索I / SUB DDQ /和I / SUB DDT /测试的组合:能量测试
作者:
Rius J.
;
Figueras J.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
36.
Digital MOS circuit partitioning with symbolic modeling
机译:
数字MOS电路分隔与符号建模
作者:
Ribas Xirgo L.
;
Carrabina Bordoll J.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
37.
High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability
机译:
具有HDTV可扩展性的单芯片MPEG-2视频编码器LSI的嵌入式软件的高速软件平台
作者:
Ochiai K.
;
Iwasaki H.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
38.
Wavefront technology mapping
机译:
波前技术映射
作者:
Stok L.
;
Iyer M.A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
39.
Self recovering controller and datapath codesign
机译:
自恢复控制器和DataPath CodeSign
作者:
Hamilton S.N.
;
Hertwig A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
40.
An efficient filter-based approach for combinational verification
机译:
基于滤波器的组合验证方法
作者:
Mukherjee R.
;
Jain J.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
41.
Polynomial methods for allocating complex components
机译:
分配复杂组件的多项式方法
作者:
Smith J.
;
De Micheli G.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
42.
On programmable memory built-in self test architectures
机译:
在可编程存储器上内置自检架构
作者:
Zarrineh K.
;
Upadhyaya S.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
43.
Operating system sensitive device driver synthesis from implementation independent protocol specification
机译:
操作系统敏感设备驱动器综合实现独立协议规范
作者:
ONils M.
;
Jantsch A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
44.
FreezeFrame: compact test generation using a frozen clock strategy
机译:
FreezeFrame:使用冷冻时钟策略的紧凑型试验
作者:
Santoso Y.
;
Merten M.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
45.
An efficient reuse system for digital circuit design
机译:
一种高效的数字电路设计重用系统
作者:
Reutter A.
;
Rosenstiel W.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
46.
Formally verified redundancy removal
机译:
正式验证冗余删除
作者:
Hendricx S.
;
Claesen L.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
47.
Parametric fault diagnosis for analog systems using functional mapping
机译:
使用功能映射模拟系统的参数故障诊断
作者:
Cherubal S.
;
Chatterjee A.
;
Institute of Electric and Electronic Engineer
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
1999年
48.
IP testing - the future differentiator?
机译:
IP测试 - 未来的差异化因素?
作者:
Eklow B.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
IP networks;
built-in self test;
error statistics;
jitter;
system-on-chip;
design for testability;
mixed signal IP testing;
Internet protocols;
processors testing;
built-in test features;
SerDes logic;
bit error rate test;
jitter test;
SOC;
system-on-chip;
IP integrator;
DFT;
design for testability;
49.
Co-processor synthesis: a new methodology for embedded software acceleration
机译:
协同处理器合成:嵌入式软件加速的新方法
作者:
Hounsell B.
;
Taylor R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
microprocessor chips;
hardware-software codesign;
embedded systems;
coprocessor synthesis;
embedded software acceleration;
configurable processor methodologies;
50.
Formal verification coverage: are the RTL-properties covering the design's architectural intent?
机译:
正式验证覆盖范围:RTL-属性是否涵盖设计的架构意图?
作者:
Basu P.
;
Das S.
;
Dasgupta P.
;
Chakrabarti P.P.
;
Mohan C.R.
;
Fix L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
formal verification;
integrated circuit design;
formal verification;
RTL-properties;
architectural intent;
RTL validation;
51.
Behavioural bitwise scheduling based on computational effort balancing
机译:
基于计算工作平衡的行为位调度
作者:
Molina M.C.
;
Ruiz-Sautua R.
;
Mendias J.M.
;
Hermida R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit design;
high level synthesis;
circuit optimisation;
scheduling;
heuristic programming;
behavioural bitwise scheduling;
computational effort balancing;
multiple precision specifications;
totally balanced schedules;
heuristic scheduling algorithm;
hardware waste minimization;
52.
Issues in implementing latency insensitive protocols
机译:
实施延迟不敏感协议的问题
作者:
Casu M.R.
;
Macchiarulo L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
protocols;
feedforward;
feedback;
system-on-chip;
trees (mathematics);
latency insensitive protocols;
functional modules;
latency insensitive design;
wrappers;
pipelined blocks;
feedforward;
feedback;
system-on-chip;
trees;
53.
SoC test scheduling with power-time tradeoff and hot spot avoidance
机译:
通过电力时间权衡和热点避免SOC测试调度
作者:
Chin J.
;
Nourani M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit testing;
system-on-chip;
scheduling;
integer programming;
linear programming;
SoC test;
test scheduling;
power-time tradeoff;
hot spot avoidance;
core-based system-on-chips;
physical power dissipation;
test time;
integer programming;
linear programming;
54.
A new self-checking sum-bit duplicated carry-select adder
机译:
一个新的自检和钻头重复携带选择加法器
作者:
Sogomonyan E.S.
;
Marienfeld D.
;
Ocheretnij V.
;
Gossel M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
adders;
parity check codes;
CAD;
logic gates;
carry logic;
self checking sum bit;
self checking carry select adder;
ripple adders;
NAND gate delay;
parity;
XOR;
exclusive OR;
CAD tool;
computer aided design;
EUROCHIP project;
64 bit carry select adder;
error detection;
64 bit;
55.
Organizing libraries of DFG patterns
机译:
组织DFG模式的图书馆
作者:
Dittmann G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
data flow graphs;
computational complexity;
application specific integrated circuits;
instruction sets;
tree searching;
DFG pattern libraries;
tree patterns;
identity operations;
computational complexity reduction;
ASIP;
instruction-set synthesis;
data-path sharing;
code generation;
56.
Timing correction and optimization with adaptive delay sequential elements
机译:
自适应延迟顺序元素定时校正和优化
作者:
Rahimi K.
;
Bridges S.
;
Diorio C.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
circuit optimisation;
shift registers;
transistors;
flip-flops;
sensitivity analysis;
circuit tuning;
timing circuits;
clocks;
timing correction;
timing optimization;
adaptive delay sequential elements;
registers;
floating gate transistors;
clock delays;
system architecture;
nonadaptive flipflops;
voltage sensitivity;
temperature sensitivity;
transistors;
circuit tuning;
clocks;
57.
Automatic scan insertion and pattern generation for asynchronous circuits
机译:
异步电路自动扫描插入和图案生成
作者:
Efthymiou A.
;
Sotiriou C.
;
Edwards D.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
asynchronous circuits;
automatic test pattern generation;
logic testing;
circuit feedback;
clocks;
automatic scan insertion;
automatic pattern generation;
asynchronous circuits;
scan latches;
global circuit feedback paths;
state-storing gates;
LSSD clocking scheme;
SOC interconnection fabric;
ATPG method;
area overhead testing;
58.
Efficient mixed-domain behavioural modelling of ferromagnetic hysteresis implemented in VHDL-AMS
机译:
VHDL-AMS中实施铁磁滞后的高效混合域行为建模
作者:
Wilson P.R.
;
Ross J.N.
;
Brown A.D.
;
Kazmierski T.
;
Baranowski J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
ferromagnetic materials;
magnetic hysteresis;
hardware description languages;
magnetisation;
Runge-Kutta methods;
polynomial approximation;
circuit simulation;
mixed-domain behavioural modelling;
ferromagnetic hysteresis;
VHDL-AMS;
mixed-signal simulations;
Jiles-Atherton model;
4th order Runga-Kutta integration;
magnetization derivative;
field strength;
SPICE;
differential equation solver;
negative BH slopes;
anhysteretic function;
polynomial approximation;
Langevin function;
integration function;
59.
Enhancing reliability of operational interconnections in FPGAs
机译:
提高FPGA中操作互连的可靠性
作者:
Fit-Florea A.
;
Halas M.
;
Kocan F.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
field programmable gate arrays;
SRAM chips;
integrated circuit reliability;
integrated circuit interconnections;
reliability improvement;
operational interconnections;
FPGA;
SRAM;
field programmable gate arrays;
MCNC benchmarks;
60.
Model-based specification and execution of embedded real-time systems
机译:
基于模型的规范和嵌入式实时系统的执行
作者:
Schattkowsky T.
;
Mueller W.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
specification languages;
virtual machines;
embedded systems;
data structures;
formal specification;
interrupts;
diagrams;
encoding;
model based specification;
model based execution;
embedded real time systems;
UML 2.0 subset;
state transition diagrams;
sequence diagrams;
interrupts;
UML virtual machine;
unified modeling language;
binary programs;
data structures;
bytecode;
61.
Power supply noise monitor for signal integrity faults
机译:
用于信号完整性故障的电源噪声监视器
作者:
Vazquez J.R.
;
de Gyvez J.P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
power supply circuits;
circuit simulation;
power cables;
integrated circuit noise;
power supply noise monitor;
signal integrity faults;
online excessive power supply noise;
power/ground lines;
62.
Polynomial abstraction for verification of sequentially implemented combinational circuits
机译:
多项式抽象,用于验证顺序实施的组合电路
作者:
Raudvere T.
;
Singh A.K.
;
Sander I.
;
Jantsch A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
combinational circuits;
circuit analysis computing;
formal verification;
circuit complexity;
polynomial abstraction;
circuit verification;
combinational circuits;
state space explosion;
verification tools;
sequential design blocks;
model checking;
design functionality;
ForSyDe methodology;
clock domain design;
design refinements verification;
63.
A macromodelling methodology for efficient high-level simulation of substrate noise generation
机译:
用于高效高级别模拟基板噪声产生的大分子调节方法
作者:
Elvira L.
;
Martorell F.
;
Aragones X.
;
Gonzalez J.L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
integrated circuit modelling;
circuit simulation;
integrated circuit noise;
substrates;
cellular arrays;
macromodelling;
high level simulation;
substrate noise generation;
SOC;
system-on-chip design;
digital standard cells;
64.
Synthesis of reversible logic
机译:
可逆逻辑的合成
作者:
Agrawal A.
;
Jha N.K.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
quantum computing;
low-power electronics;
nanotechnology;
tree searching;
circuit optimisation;
logic design;
reversible logic synthesis;
input vector;
unique output vector;
reversible function;
low power design;
quantum computing;
nanotechnology;
reversible circuits;
practical synthesis algorithm;
positive polarity Reed-Muller decomposition;
Toffoli gates network;
priority queue;
search tree;
65.
.NET framework - a solution for the next generation tools for system-level modeling and simulation
机译:
.NET Framework - 用于系统级建模和仿真的下一代工具的解决方案
作者:
Lapalme J.
;
Aboulhamid E.M.
;
Nicolescu G.
;
Charest L.
;
Boyer F.R.
;
David J.P.
;
Bois G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
systems analysis;
embedded systems;
hardware description languages;
formal specification;
storage management;
.NET framework;
system-level modeling;
system-level simulation;
system level description languages;
systems design;
SystemC;
SystemVerilog;
embedded systems;
Web-based design;
multilanguage features;
systems specification;
software components integration;
operating systems;
memory management;
automatic refinement tools;
specification models translation;
specification models annotation;
66.
A game theoretic approach to low energy wireless video streaming
机译:
低能源无线视频流的游戏理论方法
作者:
Iranli A.
;
Kihwan Choi
;
Pedram M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
video coding;
game theory;
decoding;
client-server systems;
power consumption;
game theory;
low energy video streaming;
wireless video streaming;
dynamic energy management;
client-server;
encoding aptitude;
decoding aptitude;
wireless channel;
energy consumption;
optimal energy assignment;
video quality;
system lifetime increase;
67.
Profile guided management of code partitions for embedded systems
机译:
嵌入式系统的代码分区的配置文件指导管理
作者:
Shukang Zhou
;
Childers B.R.
;
Kumar N.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
embedded systems;
buffer storage;
smart cards;
network servers;
profile guided management;
code partitions storage;
embedded systems;
embedded applications;
wireless code server;
smart cards;
network servers;
68.
Decomposition of instruction decoder for low power design
机译:
低功耗设计指令解码器的分解
作者:
Wu-An Kuo
;
TingTing Hwang
;
Wu A.C.-H.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
logic design;
decoding;
instruction sets;
microprocessor chips;
logic circuits;
reduced instruction set computing;
low-power electronics;
instruction decoder;
low power design;
microprocessors;
instruction execution;
instruction decoding;
instruction identification;
control signal generation;
data-paths;
program behavior;
power minimization;
partitioning method;
instruction-decoding circuit decomposition;
power reductions;
control unit;
69.
Are our design for testability features fault secure?
机译:
我们的可测试性设计功能故障安全吗?
作者:
Metra C.
;
Mak T.M.
;
Omana M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
design for testability;
circuit testing;
design for testability;
fault secure property;
test effectiveness;
product quality;
DFT;
70.
Adaptive prefetching for multimedia applications in embedded systems
机译:
嵌入式系统中的多媒体应用的自适应预取
作者:
Sbeyti H.
;
Niar S.
;
Eeckhout L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
storage management;
multimedia systems;
embedded systems;
cache storage;
adaptive prefetching;
multimedia applications;
embedded systems;
memory access mechanisms;
energy consumption;
data cache;
external bus transfers;
embedded microprocessor systems;
StrongArm SA1110;
Xscale like processor;
2 kByte;
8 Kbyte;
71.
Automatic scan insertion and pattern generation for asynchronous circuits
机译:
异步电路自动扫描插入和图案生成
作者:
Efthymiou A.
;
Sotiriou C.
;
Edwards D.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
asynchronous circuits;
automatic test pattern generation;
logic testing;
circuit feedback;
clocks;
automatic scan insertion;
automatic pattern generation;
asynchronous circuits;
scan latches;
global circuit feedback paths;
state-storing gates;
LSSD clocking scheme;
SOC interconnection fabric;
ATPG method;
area overhead testing;
72.
A demonstration of co-design and co-verification in a synchronous language
机译:
以同步语言的共设计和共同验证的演示
作者:
Singh S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
hardware-software codesign;
formal verification;
programming languages;
embedded systems;
field programmable gate arrays;
hardware-software codesign;
co-verification;
synchronous programming language;
Esterel technique;
embedded system design;
embedded system verification;
system level design;
Xilinx;
FPGA;
field programmable gate array;
73.
Testing of quantum dot cellular automata based designs
机译:
基于Quantum点蜂窝自动机的设计测试
作者:
Tahoori M.B.
;
Lombardi F.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
semiconductor quantum dots;
cellular automata;
circuit testing;
fault diagnosis;
design for testability;
quantum dot cellular automata testing;
conventional CMOS based designs;
complementary metal-oxide-semiconductor;
fault diagnosis;
design for testability;
74.
Realizable reduction for electromagnetically coupled RLMC interconnects
机译:
电磁耦合的RLMC互连可实现的降低
作者:
Rong Jiang
;
Chen C.C.-P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
coupled circuits;
electromagnetic coupling;
realizable RLMC reduction algorithm;
electromagnetically coupled RLMC interconnects;
interconnect circuits;
RL branch reduction;
resistance-inductance branch reduction;
RC/LC node reduction;
resistance-capacitance/inductance-capacitance node reduction;
75.
Enhancing testability of system on chips using network management protocols
机译:
使用网络管理协议提高系统对芯片的可测试性
作者:
Laouamri O.
;
Aktouf C.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
design for testability;
industrial property;
computer network management;
IP networks;
transport protocols;
testability enhancement;
SoC;
system-on-chips;
design for test;
distributed system;
intellectual properties cores;
network agents;
simple network management protocol;
TCP/IP local area networks;
76.
Synthesis of partitioned shared memory architectures for energy-sufficient multi-processor SoC
机译:
用于能量 - 足够多处理器SOC的分区共享内存架构的综合
作者:
Patel K.
;
Macii E.
;
Poncino M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
shared memory systems;
memory architecture;
system-on-chip;
multiprocessing systems;
partitioned shared memory;
memory architectures;
multiprocessor SoC;
multiprocessor systems-on-chip;
multiport memories;
parallel accesses;
energy efficiency;
shared-memory architecture;
application-driven partitioning;
shared address space;
multibank architecture;
parallel benchmarks;
dual-port memory architecture;
77.
A fast algorithm for finding maximal empty rectangles for dynamic FPGA placement
机译:
一种快速算法,用于查找动态FPGA放置的最大空矩形
作者:
Handa M.
;
Vemuri R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
field programmable gate arrays;
encoding;
computational complexity;
maximal empty rectangles;
dynamic placement;
FPGA;
rectangular tasks;
staircase data structure;
empty area;
runtime improvement;
memory requirement reduction;
time complexity;
78.
On transfer function and power consumption transient response
机译:
转移功能和功耗瞬态响应
作者:
Lipeng Cao
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
moving average processes;
power consumption;
transfer functions;
transient response;
time series;
transfer function;
power consumption;
transient response;
time series analysis techniques;
software simulation;
hardware implementation;
power monitor circuit;
79.
A macromodelling methodology for efficient high-level simulation of substrate noise generation
机译:
用于高效高级别模拟基板噪声产生的大分子调节方法
作者:
Elvira L.
;
Martorell F.
;
Aragones X.
;
Gonzalez J.L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
integrated circuit modelling;
circuit simulation;
integrated circuit noise;
substrates;
cellular arrays;
macromodelling;
high level simulation;
substrate noise generation;
SOC;
system-on-chip design;
digital standard cells;
80.
Decomposition of instruction decoder for low power design
机译:
低功耗设计指令解码器的分解
作者:
Wu-An Kuo
;
TingTing Hwang
;
Wu A.C.-H.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
logic design;
decoding;
instruction sets;
microprocessor chips;
logic circuits;
reduced instruction set computing;
low-power electronics;
instruction decoder;
low power design;
microprocessors;
instruction execution;
instruction decoding;
instruction identification;
control signal generation;
data-paths;
program behavior;
power minimization;
partitioning method;
instruction-decoding circuit decomposition;
power reductions;
control unit;
81.
MODD: a new decision diagram and representation for multiple output binary functions
机译:
MODD:多输出二进制函数的新决策图和表示
作者:
Jabir A.M.
;
Pradhan D.K.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
decision diagrams;
Boolean functions;
formal verification;
decision diagram;
multiple output binary functions;
multiple valued functions;
bits combination;
word level circuits;
memory saving;
formal verification;
82.
Operating system support for interface virtualisation of reconfigurable coprocessors
机译:
操作系统支持可重新配置协处理器的界面虚拟化
作者:
Vuletic M.
;
Righetti L.
;
Pozzi L.
;
Ienne P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
reconfigurable architectures;
system-on-chip;
field programmable gate arrays;
coprocessors;
operating systems (computers);
operating system;
interface virtualisation;
reconfigurable coprocessors;
reconfigurable systems-on-chip;
large field programmable gate arrays;
FPGA;
reconfigurable logic;
execution speedup;
virtualization layer;
interfacing complexity reduction;
portability improvement;
Linux;
83.
Automatic synthesis and simulation of continuous-time /spl Sigma//spl Delta/ modulators
机译:
连续时间/ SPL SIGMA // SPL DELTA /调制器的自动合成和仿真
作者:
Aboushady H.
;
de Lamarre L.
;
Beilleau N.
;
Louerat M.M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
sigma-delta modulation;
modulators;
circuit layout;
network synthesis;
circuit simulation;
continuous time systems;
automatic synthesis;
continuous-time modulators;
/spl Sigma/-/spl Delta/ modulators;
equation-based design methodology;
simulation-based design methodology;
high level specifications;
sigma-delta coefficients;
circuit sizing;
layout generation;
analog design environment;
CAIRO+;
third order modulator;
current-mode modulator;
84.
Co-processor synthesis: a new methodology for embedded software acceleration
机译:
协同处理器合成:嵌入式软件加速的新方法
作者:
Hounsell B.
;
Taylor R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
microprocessor chips;
hardware-software codesign;
embedded systems;
coprocessor synthesis;
embedded software acceleration;
configurable processor methodologies;
85.
Organizing libraries of DFG patterns
机译:
组织DFG模式的图书馆
作者:
Dittmann G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
data flow graphs;
computational complexity;
application specific integrated circuits;
instruction sets;
tree searching;
DFG pattern libraries;
tree patterns;
identity operations;
computational complexity reduction;
ASIP;
instruction-set synthesis;
data-path sharing;
code generation;
86.
Net and pin distribution for 3D package global routing
机译:
3D包全局路由的网络和PIN分配
作者:
Minz J.R.
;
Pathak M.
;
Sung Kyu Lim
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
printed circuits;
electronics packaging;
network routing;
circuit optimisation;
net distribution algorithm;
pin distribution algorithm;
3D package global routing;
three dimensional package global routing;
system-on-package;
PCB technology;
printed circuit board technology;
layer minimization;
wirelength minimization;
crosstalk minimization;
87.
High-performance QuIDD-based simulation of quantum circuits
机译:
基于高性能的量子电路模拟
作者:
Viamontes G.F.
;
Markov I.L.
;
Hayes J.P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
quantum gates;
decision diagrams;
circuit simulation;
quantum information decision diagram;
quantum circuits;
quantum computation;
quantum gates;
vectors modeling qubit;
complexity analysis;
Grover algorithm;
quantum search;
asymptotic runtime complexity;
quantum computer;
88.
Power supply noise monitor for signal integrity faults
机译:
用于信号完整性故障的电源噪声监视器
作者:
Vazquez J.R.
;
de Gyvez J.P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
power supply circuits;
circuit simulation;
power cables;
integrated circuit noise;
power supply noise monitor;
signal integrity faults;
online excessive power supply noise;
power/ground lines;
89.
Test compression and hardware decompression for scan-based SoCs
机译:
基于扫描的SOC的测试压缩和硬件解压缩
作者:
Wolff F.G.
;
Papachristou C.
;
McIntyre D.R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
data compression;
integrated circuit testing;
logic testing;
system-on-chip;
Huffman codes;
test compression;
hardware decompression;
scan-based SoC;
decompression architecture;
embedded cores;
download time reduction;
internal-to-ATE clock ratios;
hardware parallelism;
bounded Huffman compression;
decompression hardware tradeoffs;
RAM-based decode table;
scan chains;
test set data distributions;
90.
Data windows: a data-centric approach for query execution in memory-resident databases
机译:
数据窗口:在内存驻留数据库中查询执行的数据为中心方法
作者:
Pisharath J.
;
Choudhary A.
;
Kandemir M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
embedded systems;
query processing;
database management systems;
storage management;
data windows;
data centric approach;
query execution;
memory resident databases;
structured embedded databases;
embedded systems;
system automation;
91.
VHDL-AMS library development for pacemaker applications
机译:
VHDL-AMS用于起搏器应用的图书馆开发
作者:
Hecker B.
;
Chavassieux M.
;
Laflutte M.
;
Beguin E.
;
Lagasse L.
;
Oudinot J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
pacemakers;
defibrillators;
hardware description languages;
mixed analogue-digital integrated circuits;
simulation;
software libraries;
implantable pacemakers;
implantable defibrillators;
heart rhythm disorders;
VHDL;
hardware description language;
library development;
mixed signal ASIC;
application specific integrated circuit;
mixed signal simulator;
mentor graphics;
92.
A new self-checking sum-bit duplicated carry-select adder
机译:
一个新的自检和钻头重复携带选择加法器
作者:
Sogomonyan E.S.
;
Marienfeld D.
;
Ocheretnij V.
;
Gossel M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
adders;
parity check codes;
CAD;
logic gates;
carry logic;
self checking sum bit;
self checking carry select adder;
ripple adders;
NAND gate delay;
parity;
XOR;
exclusive OR;
CAD tool;
computer aided design;
EUROCHIP project;
64 bit carry select adder;
error detection;
64 bit;
93.
From synchronous to asynchronous: an automatic approach
机译:
从同步到异步:自动方法
作者:
Cortadella J.
;
Kondratyev A.
;
Lavagno L.
;
Lwin K.
;
Sotiriou C.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
asynchronous circuits;
synchronisation;
clocks;
asynchronous circuits;
optimized synchronous circuits;
clock distribution tree;
desynchronizing synchronous circuit;
handshaking network;
94.
CMOS structures suitable for secured hardware
机译:
CMOS结构适用于固定硬件
作者:
Guilley S.
;
Hoogvorst P.
;
Mathieu Y.
;
Pacalet R.
;
Provost J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
CMOS integrated circuits;
logic gates;
memoryless systems;
MOSFET;
memoryless CMOS structures;
complementary metal-oxide-semiconductor;
secured hardware;
unsecured electronic circuits;
physical syndromes;
information leakage;
NAND gate;
data correlation;
metal-oxide-semiconductor field effect transistor;
95.
An application of parallel discrete event simulation algorithms to mixed domain system simulation
机译:
并联离散事件仿真算法在混合域系统仿真中的应用
作者:
Reed D.K.
;
Levitan S.P.
;
Boles J.
;
Martinez J.A.
;
Chiarulli D.M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
discrete event simulation;
circuit simulation;
micromechanical devices;
synchronisation;
parallel algorithms;
parallel discrete event simulation algorithms;
mixed domain system simulation;
system level cosimulation;
mixed domain microsystem;
synchronization;
Chatoyant micro electro mechanical systems;
shared memory inter process communication;
parallel discrete event simulation techniques;
standard pipe/socket communication;
modeltech modelsim simulator;
96.
A game theoretic approach to low energy wireless video streaming
机译:
低能源无线视频流的游戏理论方法
作者:
Iranli A.
;
Kihwan Choi
;
Pedram M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
video coding;
game theory;
decoding;
client-server systems;
power consumption;
game theory;
low energy video streaming;
wireless video streaming;
dynamic energy management;
client-server;
encoding aptitude;
decoding aptitude;
wireless channel;
energy consumption;
optimal energy assignment;
video quality;
system lifetime increase;
97.
A methodology for system-level analog design space exploration
机译:
系统级模拟设计空间探索方法
作者:
De Bernardinis F.
;
Sangiovanni Vincentelli A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
analogue integrated circuits;
integrated circuit design;
system-level analog design;
design space exploration;
analog platforms;
circuit configuration sampling;
analog constraint graphs;
WCDMA amplifier;
98.
Data windows: a data-centric approach for query execution in memory-resident databases
机译:
数据窗口:在内存驻留数据库中查询执行的数据为中心方法
作者:
Pisharath J.
;
Choudhary A.
;
Kandemir M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
embedded systems;
query processing;
database management systems;
storage management;
data windows;
data centric approach;
query execution;
memory resident databases;
structured embedded databases;
embedded systems;
system automation;
99.
A unified design space for regular parallel prefix adders
机译:
常规并行前缀添加剂的统一设计空间
作者:
Ziegler M.M.
;
Stan M.R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
adders;
logic design;
digital arithmetic;
parallel prefix adders;
Kogge-Stone adder;
Han-Carlson adder;
Brent-Kung adder;
prefix adder design space;
radix dimension;
sparsity dimension;
fanout dimension;
100.
Modeling and analysis of heterogeneous industrial networks architectures
机译:
异构工业网络架构的建模与分析
作者:
Fummi F.
;
Martini S.
;
Monguzzi M.
;
Perbellini G.
;
Poncino M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
modelling;
programmable controllers;
network analysis;
simulation;
access protocols;
industrial networks architectures;
heterogeneous network modelling;
network analysis;
systemC;
PLC;
programmable logic controller;
instruction set simulator;
network simulator;
MAC protocol;
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