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IEEE/ACM International Symposium on Microarchitecture
IEEE/ACM International Symposium on Microarchitecture
召开年:
2011
召开地:
Porto Alegre(BR)
出版时间:
-
会议文集:
-
会议论文
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1.
Formally enhanced runtime verification to ensure NoC functional correctness
机译:
正式增强运行时验证,以确保NOC功能正确性
作者:
Ritesh Parikh
;
Valeria Bertacco
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Runtime;
Monitoring;
Computer bugs;
System recovery;
Hardware;
Silicon;
System-on-chip;
2.
Encore: Low-cost, fine-grained transient fault recovery
机译:
ENCORE:低成本,细粒度的瞬态故障恢复
作者:
Shuguang Feng
;
Shantanu Gupta
;
Amin Ansari
;
Scott A. Mahlke
;
David I. August
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Transient analysis;
Hardware;
Program processors;
Fault tolerance;
Fault tolerant systems;
Checkpointing;
3.
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
机译:
朝着1对多元和1次通信的理想片上面料
作者:
Tushar Krishna
;
Li-Shiuan Peh
;
Bradford M. Beckmann
;
Steven K. Reinhardt
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Coherence;
System-on-chip;
Protocols;
Routing;
Runtime;
Delays;
Wires;
4.
Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations
机译:
泡泡:通过明智的合作社增加现代仓库秤计算机的利用
作者:
Jason Mars
;
Lingjia Tang
;
Robert Hundt
;
Kevin Skadron
;
Mary Lou Soffa
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Quality of service;
Degradation;
Sensitivity;
Interference;
Servers;
Google;
Production;
5.
Preventing PCM banks from seizing too much power
机译:
防止PCM银行抓住太多的权力
作者:
Andrew Hay
;
Karin Strauss
;
Timothy Sherwood
;
Gabriel H. Loh
;
Doug Burger
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Phase change materials;
Random access memory;
Resource management;
Microprocessors;
Phase change memory;
Memory management;
6.
Hardware transactional memory for GPU architectures
机译:
GPU架构的硬件交易记忆
作者:
Wilson W. L. Fung
;
Inderpreet Singh
;
Andrew Brownsword
;
Tor M. Aamodt
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Graphics processing units;
Instruction sets;
Hardware;
System recovery;
Programming;
Synchronization;
Computer architecture;
7.
ATDetector: Improving the accuracy of a commercial data race detector by identifying address transfer
机译:
Atdetector:通过识别地址传输来提高商业数据竞争探测器的准确性
作者:
Jiaqi Zhang
;
Weiwei Xiong
;
Yang Liu
;
Soyeon Park
;
Yuanyuan Zhou
;
Zhiqiang Ma
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Detectors;
Instruction sets;
Computer bugs;
Hardware;
Servers;
Dispatching;
Open source software;
8.
Dataflow execution of sequential imperative programs on multicore architectures
机译:
DataFlow在多核架构上执行顺序势在必行程序
作者:
Gagan Gupta
;
Gurindar S. Sohi
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Programming;
Computational modeling;
Multicore processing;
Parallel processing;
Object oriented modeling;
Program processors;
9.
CoreRacer: A practical memory race recorder for multicore x86 TSO processors
机译:
Coreracer:Multicore X86 TSO处理器的实用记忆竞技器
作者:
Gilles Pokam
;
Cristiano Pereira
;
Shiliang Hu
;
Ali-Reza Adl-Tabatabai
;
Justin Gottschlich
;
Jungwoo Ha
;
Youfeng Wu
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Program processors;
Coherence;
Hardware;
Multicore processing;
Clocks;
Registers;
Proposals;
10.
Packet chaining: Efficient single-cycle allocation for on-chip networks
机译:
包链:用于片上网络的高效单周期分配
作者:
George Michelogiannakis
;
Nan Jiang
;
Daniel Becker
;
William J. Dally
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Resource management;
Throughput;
Switches;
Iron;
Ports (Computers);
Electrical engineering;
Delays;
11.
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
机译:
有效地实现非常大的模具DRAM缓存的传统块尺寸
作者:
Gabriel H. Loh
;
Mark D. Hill
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Random access memory;
Multicore processing;
Program processors;
System-on-chip;
Arrays;
Bandwidth;
Compounds;
12.
A resistive TCAM accelerator for data-intensive computing
机译:
用于数据密集型计算的电阻TCAM加速器
作者:
Qing Guo
;
Xiaochen Guo
;
Yuxin Bai
;
Engin ?pek
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Random access memory;
Computer architecture;
Microprocessors;
Magnetic tunneling;
Resistors;
Bandwidth;
Phase change materials;
13.
Bundled execution of recurring traces for energy-efficient general purpose processing
机译:
捆绑重复迹线的执行,以节能通用处理
作者:
Shantanu Gupta
;
Shuguang Feng
;
Amin Ansari
;
Scott Mahlke
;
David August
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Program processors;
Pipelines;
Latches;
Market research;
Bridges;
Computer science;
Batteries;
14.
Reducing memory interference in multicore systems via application-aware memory channel partitioning
机译:
通过应用程序感知内存通道分区减少多核系统中的内存干扰
作者:
Sai Prashanth Muralidhara
;
Lavanya Subramanian
;
Onur Mutlu
;
Mahmut Kandemir
;
Thomas Moscibroda
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Interference;
System performance;
Multicore processing;
Random access memory;
Control systems;
Bandwidth;
Partitioning algorithms;
15.
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
机译:
多保留级别STT-RAM缓存设计具有动态刷新方案
作者:
Zhenyu Sun
;
Xiuyuan Bi
;
Hai Li
;
Weng-Fai Wong
;
Zhong-Liang Ong
;
Xiaochun Zhu
;
Wenqing Wu
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Switches;
Magnetic tunneling;
Random access memory;
Resistance;
Magnetization;
Torque;
Temperature measurement;
16.
TransCom: Transforming stream communication for load balance and efficiency in networks-on-chip
机译:
Transcorm:转换用于芯片网络中负载平衡和效率的流通信
作者:
Ahmed H. Abdel-Gawad
;
Mithuna Thottethodi
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Routing;
System recovery;
Optimization;
Programming;
Hardware;
Throughput;
Program processors;
17.
A compile-time managed multi-level register file hierarchy
机译:
编译时管理的多级寄存器文件层次结构
作者:
Mark Gebhart
;
Stephen W. Keckler
;
William J. Dally
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Registers;
Instruction sets;
Graphics processing units;
Hardware;
Resource management;
18.
FeatherWeight: Low-cost optical arbitration with QoS support
机译:
羽量级:低成本的光学仲裁,QoS支持
作者:
Yan Pan
;
John Kim
;
Gokhan Memik
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Quality of service;
System-on-chip;
Bandwidth;
Silicon;
19.
System-level integrated server architectures for scale-out datacenters
机译:
用于比例数据中心的系统级集成服务器架构
作者:
Sheng Li
;
Kevin Lim
;
Paolo Faraboschi
;
Jichuan Chang
;
Parthasarathy Ranganathan
;
Norman P. Jouppi
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Servers;
Market research;
Computer architecture;
System-on-chip;
Process control;
Space exploration;
Graphics;
20.
Improving GPU performance via large warps and two-level warp scheduling
机译:
通过大扭曲和两级扭曲调度提高GPU性能
作者:
Veynu Narasiman
;
Michael Shebanow
;
Chang Joo Lee
;
Rustam Miftakhutdinov
;
Onur Mutlu
;
Yale N. Patt
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Graphics processing units;
Instruction sets;
Processor scheduling;
Pipelines;
Registers;
Benchmark testing;
Scheduling;
21.
Idempotent processor architecture
机译:
idempotent处理器体系结构
作者:
Marc de Kruijf
;
Karthikeyan Sankaralingam
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Hardware;
Out of order;
Complexity theory;
Retirement;
Computers;
Computer architecture;
22.
A new case for the TAGE branch predictor
机译:
Tage分支预测器的新案例
作者:
André Seznec
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
History;
Benchmark testing;
Hardware;
Radiation detectors;
Measurement;
Silicon;
Servers;
23.
Pack Cap: Adaptive DVFS and thread packing under power caps
机译:
Pack&Cap:Power Caps下的自适应DVFS和螺纹包装
作者:
Ryan Cochran
;
Can Hankendi
;
Ayse K. Coskun
;
Sherief Reda
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Runtime;
Instruction sets;
Multicore processing;
Power demand;
Servers;
Benchmark testing;
Energy consumption;
24.
PACMan: Prefetch-Aware Cache Management for high performance caching
机译:
Pacman:高性能缓存的预取感觉缓存管理
作者:
Carole-Jean Wu
;
Aamer Jaleel
;
Margaret Martonosi
;
Simon C. Steely
;
Joel Emer
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Prefetching;
Hardware;
Pollution;
Interference;
Servers;
Proposals;
Degradation;
25.
QSCORES: Trading dark silicon for scalable energy efficiency with quasi-specific cores
机译:
QScores:交易暗硅,可与准特定核心进行可扩展的能效
作者:
Ganesh Venkatesh
;
Jack Sampson
;
Nathan Goulding-Hotta
;
Sravanthi Kota Venkata
;
Michael Bedford Taylor
;
Steven Swanson
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Ions;
Redundancy;
26.
Pay-As-You-Go: Low-overhead hard-error correction for phase change memories
机译:
支付AS-You-Go:相位变更存储器的低开销硬误差校正
作者:
Moinuddin K. Qureshi
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Phase change materials;
Error correction;
Transient analysis;
Phase change memory;
Organizations;
Proposals;
Scalability;
27.
Parallel application memory scheduling
机译:
并行应用程序内存调度
作者:
Eiman Ebrahimi
;
Rustam Miftakhutdinov
;
Chris Fallin
;
Chang Joo Lee
;
José A. Joao
;
Onur Mutlu
;
Yale N. Patt
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Instruction sets;
Interference;
Runtime;
Synchronization;
Random access memory;
Estimation;
Scheduling algorithms;
28.
Complementing user-level coarse-grain parallelism with implicit speculative parallelism
机译:
用隐式推测平行度补充用户级粗晶行度
作者:
Nikolas Ioannou
;
Marcelo Cintra
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Informatics;
Servers;
Lead;
Writing;
Acceleration;
Hardware;
Routing;
29.
A systematic methodology to develop resilient cache coherence protocols
机译:
一种开发弹性高速缓存相干协议的系统方法
作者:
Konstantinos Aisopos
;
Li-Shiuan Peh
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2011年
关键词:
Protocols;
Coherence;
Transient analysis;
Reliability;
Systematics;
Hardware;
Resilience;
30.
Execution Drafting: Energy Efficiency through Computation Deduplication
机译:
执行起草:通过计算重复数据删除能效
作者:
Mckeown Michael
;
Balkind Jonathan
;
Wentzlaff David
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
computer centres;
multi-threading;
pipeline processing;
power aware computing;
Apache Web server;
CPU;
OpenSPARC T1 core;
architectural technique;
computation centralization;
computation deduplication;
data center;
drafted instruction decoding;
drafted instructions;
energy efficiency;
energy reduction;
energy saving;
execution drafting;
hardware overhead analysis;
hardware overhead drafting;
hardware technique evaluation;
identical instruction execution;
latency improvement;
loading constants;
multithreaded core;
pipeline commit stage;
pipeline execution stage;
switching reduction;
throughput reduction;
Hardware;
Instruction sets;
Pipelines;
Servers;
Switches;
Synchronization;
Throughput;
Cloud Computing;
Computation Deduplication;
Data Center Computing;
Energy Efficiency;
Energy Efficient Computing;
Microarchitecture;
Multithreading;
31.
PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research
机译:
Pymtl:垂直集成计算机架构研究的统一框架
作者:
Lockhart Derek
;
Zibrat Gary
;
Batten Christopher
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
C++ language;
computer architecture;
program compilers;
program interpreters;
CL;
FL;
JIT specialization approach;
JIT specialization engine;
PyMTL;
PyPy;
Python interpreter;
Python programming language;
RTL modeling;
Sim JIT;
concurrent-structural modeling;
cycle-level modeling;
design patterns;
domain-specific embedded language;
functional-level modeling;
hybrid JIT compilation;
meta-tracing JIT compiler;
optimized C++;
performance-productivity gap;
register-transfer-level modeling;
unified framework;
unique languages;
vertically integrated computer architecture research;
vertically integrated research methodology;
Computational modeling;
Computer architecture;
Computers;
Hardware;
Hardware design languages;
Object oriented modeling;
Productivity;
32.
Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution
机译:
均衡器:GPU资源的动态调整以实现高效执行
作者:
Sethia Ankit
;
Mahlke Scott
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
energy conservation;
graphics processing units;
resource allocation;
Equalizer;
GPU resource dynamic tuning;
bottleneck resource;
concurrent threads;
core frequency;
energy saving;
hardware runtime system;
kernel characteristics;
kernel resource requirements;
memory frequency;
on-chip concurrency;
Equalizers;
Graphics processing units;
Instruction sets;
Kernel;
Memory management;
Pipelines;
Runtime;
Dynamic Voltage and Frequency Scaling;
GPGPUs;
Resource Utilization;
Runtime System;
33.
Futility Scaling: High-Associativity Cache Partitioning
机译:
无用数缩放:高关联高速缓存分区
作者:
Ruisheng Wang
;
Lizhong Chen
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cache storage;
microprocessor chips;
multiprocessing systems;
performance evaluation;
LFU;
LRU;
PriSM;
Vantage;
associativity degradation;
destructive interference;
feedback-based implementation;
futility scaling;
high-associativity cache partitioning;
many-core CMP;
replacement-based cache partitioning scheme;
resource efficiency;
system performance;
Aerospace electronics;
Benchmark testing;
Degradation;
Optimized production technology;
Partitioning algorithms;
Quality of service;
Resource management;
34.
Harnessing Soft Computations for Low-Budget Fault Tolerance
机译:
利用低预算容错的软计算
作者:
Khudia Daya Shanker
;
Mahlke Scott
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
program compilers;
software fault tolerance;
compiler-based approach;
fault tolerant computations;
full duplication scheme;
low-budget fault tolerance;
performance overhead;
program macrooperation;
soft computations;
soft workloads;
software-only transient fault detection;
user-visible silent data corruptions;
Benchmark testing;
Circuit faults;
Decoding;
Fault tolerance;
Fault tolerant systems;
Multimedia communication;
Optimization;
Compiler Analysis;
Soft Errors;
35.
GPUMech: GPU Performance Modeling Technique Based on Interval Analysis
机译:
GPUMECH:基于间隔分析的GPU性能建模技术
作者:
Jen-Cheng Huang
;
Joo Hwan Lee
;
Hyesoon Kim
;
Lee Hsien-Hsin S.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
graphics processing units;
multi-threading;
performance evaluation;
CPI stacks;
GPU architectures;
GPU performance modeling technique;
GPUMech;
greedy-then-oldest policy;
interval analysis;
memory divergence;
multithreading;
resource contentions;
round-robin scheduling policy;
timing simulator;
Analytical models;
Computer architecture;
Graphics processing units;
Kernel;
Multithreading;
Timing;
Vectors;
GPGPU;
interval analysis;
performance modeling;
simulation;
36.
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth
机译:
Bi-Modal DRAM缓存:提高命中率,打击延迟和带宽
作者:
Gulur Nagendra
;
Mehendale Mahesh
;
Manikantan R.
;
Govindarajan R.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
DRAM chips;
bandwidth allocation;
cache storage;
meta data;
performance evaluation;
ANTT;
DRAM cache capacity;
DRAM cache organization;
SRAM based way locator;
average normalized turnaround time;
bimodal DRAM cache;
cache hit latency;
flexible stacked DRAM cache organization;
hit latency;
hit rate;
metadata;
off-chip bandwidth wastage;
off-chip memory bandwidth consumption;
performance improvement;
tag storage overhead;
tags-in-SRAM;
Bandwidth;
Layout;
Memory management;
Organizations;
Random access memory;
Stacking;
Vectors;
3D Stacking;
CMP;
DRAM;
DRAM cache;
Memory Systems;
37.
Specializing Compiler Optimizations through Programmable Composition for Dense Matrix Computations
机译:
通过用于密集矩阵计算的可编程组合来专用编译器优化
作者:
Qing Yi
;
Qian Wang
;
Huimin Cui
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
mathematics computing;
matrix algebra;
optimising compilers;
pattern recognition;
coordination handles;
dense matrix computation;
dynamic tags;
general purpose compilers;
general-purpose compiler optimization;
pattern recognition;
programmable composition;
source-level analysis;
Arrays;
Kernel;
Libraries;
Optimization;
Pattern recognition;
Runtime;
Safety;
Automatic programming;
Computer science;
Computers and information processing;
Programming;
38.
Adaptive Cache Management for Energy-Efficient GPU Computing
机译:
节能GPU计算的自适应缓存管理
作者:
Xuhao Chen
;
Li-Wen Chang
;
Rodrigues Christopher /I/.
;
Jie Lv
;
Zhiying Wang
;
Wen-Mei Hwu
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cache storage;
energy conservation;
graphics processing units;
multi-threading;
multiprocessing systems;
resource allocation;
CPU cache management policies;
GPU architectures;
SIMT execution model;
adaptive cache management;
baseline GPU architecture;
bypass policy;
cache contention;
cache hierarchy;
cache sensitive benchmarks;
energy-efficient GPU computing;
harmonic mean IPC;
memory access patterns;
memory latency;
multicore systems;
multithreading;
optimal static warp throttling;
resource congestion;
spatial locality;
temporal locality;
throughput-oriented execution model;
Bandwidth;
Benchmark testing;
Graphics processing units;
Hardware;
Instruction sets;
Multithreading;
System-on-chip;
GPGPU;
bypass;
cache management;
warp throttling;
39.
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists
机译:
使用细粮五金工作室加速GPGPU上的不规则算法
作者:
Ji Yun Kim
;
Batten Christopher
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
application program interfaces;
benchmark testing;
graphics processing units;
multiprocessing systems;
resource allocation;
virtualisation;
LonestarGPU benchmark suite;
baseline GPGPU;
cycle-level simulator;
data-driven implementations;
fine-grain hardware worklists;
general-purpose graphics-processing units;
hardware worklist;
irregular algorithm acceleration;
irregular algorithm implementation;
load balancing improvement;
marginal area overhead;
memory contention;
memory-access irregularity;
shared worklist software API;
virtualization mechanism;
work redistribution schemes;
work spilling;
Benchmark testing;
Hardware;
Heuristic algorithms;
Instruction sets;
Kernel;
Load management;
Optimization;
40.
Multi-GPU System Design with Memory Networks
机译:
具有内存网络的多GPU系统设计
作者:
Gwangsun Kim
;
Minseok Lee
;
Jiyun Jeong
;
Kim Jung-Ho
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
graphics processing units;
hypercube networks;
network topology;
random-access storage;
storage management;
CMN;
CPU memory network;
GMN;
GPU memory network;
GPU-host CPU communication;
HMC;
SKE;
UMN;
data communication;
data sharing;
hybrid memory cubes;
multiGPU memory management;
multiGPU programming;
multiGPU system design;
overlay network organization;
remote GPU memory;
scalable kernel execution;
sliced flattened butterfly topology;
unified memory network;
Bandwidth;
Graphics processing units;
Kernel;
Memory management;
Network topology;
Runtime;
Topology;
Flattened butterfly;
Hybrid Memory Cubes;
Memory network;
41.
Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks
机译:
高效的内存虚拟化:减少嵌套页面的维度
作者:
Gandhi Jayneel
;
Basu Anirban
;
Hill Mark D.
;
Swift Michael M.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
Linux;
buffer storage;
virtual machines;
virtualisation;
2D page walk;
KVM;
Linux;
TLB;
VMM direct mode;
big-memory workloads;
dimensionality reduction;
direct segments;
dual direct mode;
escape filter;
guest physical address;
guest virtual address;
host physical address;
kernel-based virtual machine;
memory virtualization;
near-zero translation overhead;
nested page walks;
self-ballooning;
translation look aside buffer;
virtual machine monitors;
virtualized address translation;
virtualized operation modes;
Microarchitecture;
translation lookaside buffer;
virtual machines;
virtual memory;
virtualization;
42.
Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers
机译:
Protean代码:实现仓库秤计算机的近免费在线代码转换
作者:
Laurenzano Michael /A/.
;
Yunqi Zhang
;
Lingjia Tang
;
Mars Jason
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
computer centres;
instruction sets;
program compilers;
quality of service;
IR;
LLVM;
PC3D;
Protean Code for Cache Contention in Datacenters;
Protean code compiler;
QoS;
WSC;
application quality of service;
arbitrary compiler transformations;
commodity hardware;
contention mitigation runtime techniques;
dynamic compiler;
high-level semantic information;
instruction set features;
near-free online code transformation;
rampant dynamism;
warehouse scale computers;
Dynamic compiler;
Hardware;
Monitoring;
Optimization;
Program processors;
Quality of service;
cache;
compiler;
datacenter;
dynamic compiler;
optimization;
resource sharing;
warehouse scale computer;
43.
SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers
机译:
SMITE:精确的QoS预测真实系统SMT处理器,以提高仓库秤计算机的利用
作者:
Yunqi Zhang
;
Laurenzano Michael /A/.
;
Mars Jason
;
Lingjia Tang
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
computer centres;
multi-threading;
quality of service;
regression analysis;
shared memory systems;
CMP;
CloudSuite;
QoS prediction;
Rulers;
SMT architectures;
SMT co-location;
SMiTe;
SPEC CPU2006;
WSCs;
application contentiousness;
application sensitivity;
chip multiprocessor;
performance interference;
quality of service;
real-system SMT processors;
real-system commodity processors;
regression model;
resource sharing behaviors;
shared resource multidimensional space;
simultaneous multithreading;
software stressors;
warehouse scale computers;
Degradation;
Interference;
Multicore processing;
Program processors;
Quality of service;
Sensitivity;
Servers;
datacenter;
quality of service;
simultaneous multithreading;
warehouse scale computer;
44.
Transparent Hardware Management of Stacked DRAM as Part of Memory
机译:
堆叠DRAM的透明硬件管理作为内存的一部分
作者:
Jaewoong Sim
;
Alameldeen Alaa R.
;
Chishti Zeshan
;
Wilkerson Chris
;
Hyesoon Kim
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
DRAM chips;
bandwidth allocation;
cache storage;
OS-based dynamic remapping policy;
OS-managed heterogeneous memory system;
PoM architecture;
die-stacked DRAM;
heterogeneous memory system;
integrated memory;
off-chip memory;
on-die memory structure integration;
part-of-memory architecture;
static mapping;
transparent hardware management;
usage-monitoring hardware;
Hardware;
Memory management;
Motion segmentation;
Radiation detectors;
Random access memory;
Resource management;
Die-Stacking;
Hardware Management;
Heterogeneous Memory;
Stacked DRAM;
45.
Managing GPU Concurrency in Heterogeneous Architectures
机译:
在异构架构中管理GPU并发性
作者:
Kayiran Onur
;
Nachiappan Nachiappan Chidambaram
;
Jog Adwait
;
Ausavarungnirun Rachata
;
Kandemir Mahmut T.
;
Loh Gabriel H.
;
Mutlu Onur
;
Das Chita R.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
concurrency control;
graphics processing units;
multi-threading;
parallel architectures;
performance evaluation;
resource allocation;
CM-BAL;
CM-CPU;
CPU performance;
GPU core state;
GPU interference;
GPU performance;
GPU-based concurrency management techniques;
TLP;
general-purpose CPU;
heterogeneous architectures;
heterogeneous systems;
homogeneous architectures;
integrated concurrency management strategy;
network congestion information;
resource utilization;
shared hardware resources;
shared resource interference minimization;
system-wide memory;
thread-level parallelism;
throughput-optimized GPU;
Bandwidth;
Central Processing Unit;
Computer architecture;
Concurrent computing;
Graphics processing units;
Resource management;
System performance;
CPU-GPU;
GPUs;
concurrency;
heterogeneous architectures;
resource management;
scheduling;
thread-level parallelism;
46.
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks
机译:
通过可重新配置的配电网络实现现实的微粒电压缩放
作者:
Godycki Waclaw
;
Torng Christopher
;
Bukreyev Ivan
;
Apsel Alyssa
;
Batten Christopher
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
distribution networks;
energy conservation;
multi-threading;
power aware computing;
switched capacitor networks;
system-on-chip;
voltage regulators;
FG-SYNC+;
FGVS;
RPDN;
activity imbalance;
architecture-level modeling;
area-power efficiency;
circuit-level modeling;
dynamic voltage-frequency scaling controller;
energy efficiency;
fine-grain synchronization controller;
integration complexity;
multithreaded applications;
on-chip switched-capacitor regulators;
on-chip voltage regulation;
power density;
power efficiency;
realistic fine-grain voltage scaling;
reconfigurable power distribution networks;
response time;
system-on-chip;
vertically integrated research methodology;
voltage regulator monolithic integration;
Regulators;
Switches;
Synchronization;
System-on-chip;
Time factors;
Time-frequency analysis;
Voltage control;
DVFS;
on-chip voltage regulation;
power distribution networks;
47.
Random Fill Cache Architecture
机译:
随机填充缓存架构
作者:
Fangfei Liu
;
Lee Ruby B.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cache storage;
cryptography;
memory architecture;
cache designs;
cache side-channel attacks;
confidentiality breaches;
configurable neighborhood window;
contention based attacks;
encryption keys;
fake services;
fundamental demand fetch policy;
impersonation attacks;
information-theoretic security;
random fill cache architecture;
reuse based attacks;
Computer architecture;
Encryption;
Hardware;
Timing;
cache;
cache collision attacks;
computer architecture;
secure caches;
security;
side channel attacks;
48.
Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults
机译:
计算空间多位瞬态故障的架构漏洞因素
作者:
Wilkening Mark
;
Sridharan Vilas
;
Si Li
;
Previlon Fritz
;
Gurumurthi Sudhanva
;
Kaeli David R.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
SRAM chips;
fault tolerant computing;
graphics processing units;
microprocessor chips;
reliability;
AVF analysis;
DUE;
GPU vector register file;
SDC MB-AVF;
SRAM faults;
architectural vulnerability factors;
detected uncorrected errors;
fault modeling;
microprocessors;
multibit AVF analysis approach;
reliability;
silent data corruption MB-AVF;
single-bit transient faults;
spatial multibit transient faults;
static random-access memory faults;
Analytical models;
Error analysis;
Hardware;
Life estimation;
Random access memory;
Reliability;
Transient analysis;
fault tolerance;
reliability;
soft errors;
49.
Dodec: Random-Link, Low-Radix On-Chip Networks
机译:
Dodec:随机链接,低基数片上网
作者:
Haofan Yang
;
Tripathi Jyoti
;
Jerger Natalie Enright
;
Gibson Dan
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
digital arithmetic;
integrated circuit design;
multiprocessing systems;
network routing;
network topology;
network-on-chip;
resource allocation;
Dodec;
PARSEC;
chip design;
load balancing;
low-radix on-chip network;
many-core architectures;
message latency;
network cost;
network diameter;
network topology;
random on-chip topology;
random-link on-chip network;
randomized low-radix router connections;
router microarchitecture;
Complexity theory;
Network topology;
Optimization;
Routing;
System recovery;
System-on-chip;
Topology;
50.
Continuous, Low Overhead, Run-Time Validation of Program Executions
机译:
连续,低开销,程序执行的运行时间验证
作者:
Aktas Erdem
;
Afram Furat
;
Ghose Kanad
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
benchmark testing;
program compilers;
program testing;
program verification;
trusted computing;
ISA support;
REV;
SPEC 2006 benchmarks;
X86 ISA;
code injection;
contemporary out-of-order processor;
control flow path;
control flow signature based authentication;
embedded systems;
illegal dynamic program module linking;
jump-oriented programming;
microarchitectural standpoint;
out-of-order cores;
performance overhead;
preexecution code integrity validations;
program executions;
return-oriented programming;
run-time execution validator;
run-time validation;
software testing;
trustworthy systems;
Authentication;
Cryptography;
Hardware;
Kernel;
Out of order;
Pipelines;
Computer Security;
Control-Flow Integrity;
Control-Flow Validation;
Hardware Security;
Secure Execution;
Trusted Computing;
51.
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
机译:
Civeo:具有主要内存容量和硬件管理缓存的能力的两级内存组织
作者:
ChiaChen Chou
;
Jaleel Aamer
;
Qureshi Moinuddin K.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
DRAM chips;
cache storage;
table lookup;
CAMEO;
LLT look-up;
cache-like memory organization;
data locality;
hardware-based fine-granularity;
hardware-managed cache;
idealized memory system;
line location predictor;
line location table;
main memory capacity;
memory access;
memory address space;
offchip memory;
stacked DRAM;
two-level memory organization;
Bandwidth;
Benchmark testing;
Hardware;
Memory management;
Organizations;
Random access memory;
Software;
cache;
memory;
stacked DRAM;
52.
Short-Circuiting Memory Traffic in Handheld Platforms
机译:
手持平台中的短路内存流量
作者:
Yedlapalli Praveen
;
Nachiappan Nachiappan Chidambaram
;
Soundararajan Niranjan
;
Sivasubramaniam Anand
;
Kandemir Mahmut T.
;
Das Chita R.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
buffer storage;
mobile computing;
notebook computers;
power aware computing;
IP-IP short-circuiting;
IP-to-IP data reuse distances;
flow-buffering;
frame granularity;
frame-based data;
handheld platforms;
memory subsystem;
memory traffic short-circuiting;
performance scaling;
Bandwidth;
Cameras;
Computer aided manufacturing;
Hardware;
IP networks;
Random access memory;
System-on-chip;
Buffer;
Frames;
Locality;
Memory;
Mobile;
SoC;
53.
Arbitrary Modulus Indexing
机译:
任意模量索引
作者:
Diamond Jeffrey R.
;
Fussell Donald S.
;
Keckler Stephen W.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cache storage;
graphics processing units;
indexing;
AMI;
address mapping;
aggressive baseline system;
arbitrary modulus indexing;
cache locations;
data locations;
high performance processors;
local high speed memory banks;
memory access patterns;
memory intensive benchmark;
memory system bottleneck;
memory-intensive workload;
prime moduli;
processor computation rate;
replay-style GPU architecture;
Adders;
Arrays;
Graphics processing units;
Hardware;
Indexing;
GPU caches;
fast division and modulus;
index schemes;
prime-banking;
replay architectures;
54.
Load Value Approximation
机译:
负载值近似
作者:
San Miguel Joshua
;
Badr Mario
;
Jerger Natalie Enright
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
fault tolerant computing;
microprocessor chips;
performance evaluation;
power aware computing;
PARSEC workloads;
approximate computing;
energy-efficiency;
error tolerance;
load instructions;
load value approximation;
machine learning;
memory accesses;
microarchitectural technique;
multimedia processing;
processor performance;
Accuracy;
Approximation methods;
Delays;
Estimation;
History;
Prefetching;
Radiation detectors;
55.
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models
机译:
管道检查:指定和验证内存一致性模型的微架立强制
作者:
Lustig Daniel
;
Pellauer Michael
;
Martonosi Margaret
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
formal specification;
multiprocessing systems;
pipeline processing;
program verification;
software architecture;
μhb graph;
O3 pipeline;
OpenSPARC T2;
PipeCheck;
architectural specification;
architecturally-specified consistency model;
architecture-level analysis techniques;
formal architecture-level definitions;
gem5 simulator;
memory consistency models;
memory instruction;
memory location;
microarchitectural enforcement specification;
microarchitectural enforcement verification;
microarchitectural optimizations;
microarchitecturally-happens-before graph;
microarchitecture space;
open-source pipelines;
pipeline stage;
preserved-program order;
speculative load reordering;
Buffer storage;
Load modeling;
Mathematical model;
Microarchitecture;
Pipelines;
Program processors;
Radio frequency;
56.
Keynote Abstracts
机译:
主题演讲摘要
作者:
Muller Mathias
;
Mudge Trevor
;
Smith James E.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
Internet of Things;
brain models;
cloud computing;
computer architecture;
power aware computing;
Internet of Things;
IoT;
Moore's law;
brain computational paradigm;
cloud services;
efficiency analysis;
microarchitecture;
57.
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration
机译:
高升:具有单周期仲裁的3D集成的高基数开关
作者:
Jeloka Supreet
;
Das Ratan
;
Dreslinski Ronald G.
;
Mudge Trevor
;
Blaauw D.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
digital arithmetic;
multiprocessor interconnection networks;
network routing;
3D integration;
Hi-Rise;
class-based arbitration scheme;
data routing;
die stacked layer;
flat 2D switch;
hierarchical 3D switch;
high-radix switch;
interconnect;
single-cycle arbitration;
switching fabric;
uniform random traffic;
Delays;
Fabrics;
Radiation detectors;
Silicon;
Switches;
Three-dimensional displays;
Throughput;
3D Integration;
Arbitration;
High-Radix Switch;
58.
CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware
机译:
CC-Hunter:在共享处理器硬件上揭示隐蔽定时频道
作者:
Jie Chen
;
Venkataramani Guru
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
security of data;
CC-Hunter;
Chanter;
covert timing channel uncovering;
illegitimate communication channel;
information leakage;
malicious hackers;
micro architecture-level framework;
sensitive information safeguarding;
shared processor hardware;
timing modulation;
Bandwidth;
Computers;
Hardware;
Histograms;
Software;
Timing;
Trojan horses;
Algorithms;
Covert timing channels;
Detection;
Shared hardware;
59.
Locality-Aware Mapping of Nested Parallel Patterns on GPUs
机译:
GPU上嵌套并行模式的位置感知映射
作者:
Hyoukjoong Lee
;
Brown Kevin J.
;
Sujeeth Arvind K.
;
Rompf Tiark
;
Olukotun Kunle
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
graphics processing units;
optimising compilers;
parallel processing;
shared memory systems;
1D mapping;
2D mapping;
GPU hardware;
GPU kernels;
GPU-specific hard constraints;
GPU-specific soft constraints;
block size parameterization;
compiler optimizations;
general analysis framework;
high level computation patterns;
higher level languages;
locality-aware mapping;
logical multidimensional domain;
nested parallel pattern;
parallel semantics encoding;
parallelism degree;
pattern mapping;
shared memory;
Graphics processing units;
Hardware;
Instruction sets;
Kernel;
Optimization;
Parallel processing;
Programming;
60.
PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration
机译:
PPEP:在线性能,电力和能量预测框架和DVFS空间探索
作者:
Bo Su
;
Junli Gu
;
Li Shen
;
Wei Huang
;
Greathouse Joseph L.
;
Zhiying Wang
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
energy conservation;
power aware computing;
AMD CPU;
CPI model;
DVFS space exploration;
PPEP;
cycles-per-instruction model;
dynamic voltage and frequency scaling;
energy saving;
iterative algorithm;
online performance power and energy prediction framework;
per-core power model;
power capping mechanism;
reactive algorithm;
voltage-frequency states;
Benchmark testing;
Hardware;
Power measurement;
Predictive models;
Program processors;
Radiation detectors;
Temperature measurement;
61.
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
机译:
在数据并行架构上探索SPMD发散管理的设计空间
作者:
Yunsup Lee
;
Grover Vinod
;
Krashinsky Ronny
;
Stephenson Mark
;
Keckler Stephen W.
;
Asanovic Krste
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
graphics processing units;
hardware-software codesign;
parallel architectures;
program compilers;
GPU silicon;
SPMD divergence management;
complex control-flow constructs;
data-parallel architectures;
design space;
divergent control paths;
microarchitecture;
parallel threads;
predication-based approach;
predication-only architecture;
production compiler;
single program multiple-data language;
single-program multiple-data languages;
software-hardware divergence management;
software-only approach;
Computer architecture;
Hardware;
Optimization;
Registers;
Software;
Support vector machines;
Vectors;
Control-Flow Divergence;
GPU;
Predication;
Vector Processors;
62.
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities
机译:
多核处理器的电压噪声:经验表征和优化机会
作者:
Bertran Ramon
;
Buyuktosunoglu Alper
;
Bose Pradip
;
Slegel Timothy J.
;
Salem Gerard
;
Carey Sean
;
Rizzolo Richard F.
;
Strach Thomas
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
mainframes;
multiprocessing systems;
noise measurement;
alignment degree;
dynamic voltage guard banding;
empirical characterization;
event synchronization;
high-end processor based systems;
mainframe class multicoreprocessor;
multicore chip;
noise events;
noise mitigation;
noise propagation;
noise stress mark generation;
optimization opportunities;
post-silicon setting;
stimulus sequence frequency;
supply current delta;
systematic methodology;
voltage noise direct measurement-based characterization;
workload mappings;
Multicore processing;
Noise;
Noise measurement;
Reliability;
Resonant frequency;
Synchronization;
Voltage measurement;
dI/dt;
dynamic guardbanding;
inductive noise;
multi-core hardware measurements;
noise-aware workload mapping;
stressmark generation;
voltage droop;
63.
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems
机译:
公司:对持久存储器系统的公平和高性能内存控制
作者:
Jishen Zhao
;
Mutlu Onur
;
Yuan Xie
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
parallel processing;
random-access storage;
scheduling;
system buses;
FIRM;
bank-level parallelism;
bus turnaround;
byte-addressable nonvolatile memories;
contiguous memory region;
data duplication;
data persistence;
fair memory control;
high-performance memory control;
memory access characteristics;
memory bandwidth utilization;
memory channel;
memory scheduler design;
memory scheduling scheme;
ordering control;
persistent memory systems;
write queue drain;
write requests;
write traffic;
Bandwidth;
Computer crashes;
Delays;
Memory management;
Nonvolatile memory;
Parallel processing;
Random access memory;
data persistence;
fairness;
memory interference;
memory scheduling;
nonvolatile memory;
persistent memory;
64.
BuMP: Bulk Memory Access Prediction and Streaming
机译:
凹凸:批量内存访问预测和流媒体
作者:
Volos Stavros
;
Picorel Javier
;
Falsafi Babak
;
Grot Boris
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
DRAM chips;
cache storage;
computer centres;
paged storage;
power aware computing;
BuMP;
DRAM chips;
DRAM energy per access;
DRAM page activations;
Dennard scaling;
bulk memory access prediction;
bulk memory access streaming;
bulk transfer operations;
dirty LLC eviction;
energy efficiency;
high-density DRAM pages;
lean-core server processors;
low-density pages;
multiple row buffer access;
server efficiency;
server energy consumption;
server power;
supply voltage scaling;
virtually unpredictable reference patterns;
Energy efficiency;
Indexes;
Memory management;
Program processors;
Random access memory;
Servers;
DRAM;
energy efficiency;
memory streaming;
row buffer;
65.
RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks
机译:
RPStacks:使用代表失速事件堆栈的快速准确的处理器设计空间探索
作者:
Jaewon Lee
;
Hanhwi Jang
;
Jangwoo Kim
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
integrated circuit design;
microprocessor chips;
performance evaluation;
CPU architects;
RpStacks;
design point key performance bottlenecks;
exploration overhead;
latency adjustments;
performance estimation;
performance predictions;
performance-critical events;
processor design space exploration method;
stall-event composition;
stall-event stacks;
Acceleration;
Accuracy;
Analytical models;
Complexity theory;
Design methodology;
Space exploration;
Timing;
Design space exploration;
Performance analysis;
Simulation;
66.
Skewed Compressed Caches
机译:
偏斜的压缩缓存
作者:
Sardashti Somayeh
;
Seznec Andre
;
Wood David /A/.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cache storage;
data compression;
SCC;
direct tag-data mapping;
hardware compressed cache;
internal fragmentation reduction;
skewed associative mapping;
skewed compressed caches;
sparse super-block tags;
tag overhead reduction;
Arrays;
Complexity theory;
Compression algorithms;
Computers;
Educational institutions;
Hardware;
Indexes;
cache design;
compression;
energy;
performance;
67.
Compiler Support for Optimizing Memory Bank-Level Parallelism
机译:
编译器支持优化内存库级并行性
作者:
Wei Ding
;
Guttman Diana
;
Kandemir Mahmut
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cache storage;
multi-threading;
multiprocessing systems;
optimising compilers;
program control structures;
scheduling;
BLP optimization scheme;
cache data locality;
cache miss equations;
compiler support;
compiler-based optimization schemes;
last-level cache;
loop tile scheduling;
memory access latency;
memory bank-level parallelism optimization;
memory controller-level parallelism;
multicores;
multithreaded applications;
row-buffer locality;
Arrays;
Optimization;
Parallel processing;
Random access memory;
Schedules;
Scheduling;
Vectors;
bank-level parallelism;
compiler;
memory controller-level parallelism;
row-buffer locality;
68.
A Front-End Execution Architecture for High Energy Efficiency
机译:
高能效的前端执行架构
作者:
Shioya Ryota
;
Goshima Masahiro
;
Ando Hideki
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
multiprocessing systems;
parallel architectures;
power aware computing;
processor scheduling;
satellite computers;
ARM big.LITTLE architecture;
FXA;
IXU;
NOP;
OXU;
SPECCPU INT 2006 benchmark suite;
application processors;
bypass network;
dynamic instruction scheduling logic;
energy consumption reduction;
energy-delay product;
execution core;
front-end execution architecture;
functional units;
geometric mean;
high-energy efficiency;
in-order execution unit;
instruction fetching;
issue queue;
mobile devices;
not-ready instructions;
out-of-order execution unit;
out-of-order superscalar processors;
performance improvements;
performance/energy ratio;
Complexity theory;
Degradation;
Energy consumption;
Out of order;
Performance evaluation;
Pipelines;
Core Microarchitecture;
Energy Efficiency;
Hybrid In-Order/Out-of-Order Core;
69.
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors
机译:
B-fetch:芯片多处理器的分支预测导向预取预取
作者:
Kadjo David
;
Kim Jung-Ho
;
Sharma Parmanand
;
Panda Reena
;
Gratz Paul
;
Jimenez Daniel
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
VLSI;
cache storage;
microprocessor chips;
multiprocessing systems;
multiprogramming;
power aware computing;
B-Fetch;
CMP design;
LLC;
VLSI power scaling;
baseline system;
branch prediction directed prefetching;
cache hierarchies;
cache pollution effects;
chip-multiprocessor design;
concurrent processes;
control flow prediction;
high-overhead and high accuracy data prefetchers;
last-level cache;
light-weight prefetcher;
low-overhead and low accuracy data prefetchers;
memory wall;
multiapplication workloads;
multiprogrammed workloads;
single-threaded workloads;
Accuracy;
Benchmark testing;
Engines;
Hardware;
Pipelines;
Prefetching;
Registers;
Bfetch;
Branch Prediction;
Chip-Multiprocessors;
Data Cache;
Prefetching;
70.
PORPLE: An Extensible Optimizer for Portable Data Placement on GPU
机译:
Porple:GPU上的可扩展优化器,可用于GPU上的便携式数据放置
作者:
Guoyang Chen
;
Bo Wu
;
Dong Li
;
Xipeng Shen
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
data handling;
graphics processing units;
memory architecture;
program compilers;
specification languages;
GPU program;
PORPLE;
architecture complexity;
data access patterns;
extensible optimizer;
memory architectures;
memory description;
mini specification language;
portable data placement;
runtime data placer;
runtime profiling;
source-to-source compiler;
Arrays;
Engines;
Graphics processing units;
Instruction sets;
Kernel;
Runtime;
cache;
compiler;
data placement;
hardware specification language;
71.
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
机译:
硅插入器系统的NOC架构:为什么可以免费支付更多电线(从您的插入器)免费?
作者:
Jerger Natalie Enright
;
Kannan Ajaykumar
;
Zimo Li
;
Loh Gabriel H.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
DRAM chips;
microprocessor chips;
monolithic integrated circuits;
multiprocessing systems;
multiprocessor interconnection networks;
network routing;
network-on-chip;
3D stacking DRAM;
NoC architectures;
asymmetric organization;
in-package memory capacity;
indirect network organizations;
interposer overall routing capacity;
memory integration;
multicore chip;
network-on-chip;
point-to-point interconnects;
routing resources;
silicon interposer systems;
silicon interposer technology;
Bandwidth;
Metals;
Multicore processing;
Routing;
Silicon;
Stacking;
Topology;
72.
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
机译:
unison缓存:可扩展且有效的模堆DRAM缓存
作者:
Jevdjic Djordje
;
Loh Gabriel H.
;
Kaynak Cansu
;
Falsafi Babak
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
DRAM chips;
SRAM chips;
cache storage;
paged storage;
Alloy Cache approach;
DRAM access;
SRAM-based tags;
Unison cache;
bandwidth wall;
block-based data management;
die-stacked DRAM cache;
footprint cache design;
lookup latencies;
manycore servers;
memory latency;
multigigabyte stacked DRAM caches;
off-chip bandwidth;
off-chip traffic;
on-chip tag storage;
page granularity;
page-based DRAM caches;
page-based data management;
page-sized cache allocation units;
server workloads;
stacked-DRAM capacities;
Bandwidth;
Metals;
Organizations;
Random access memory;
Resource management;
Servers;
System-on-chip;
3D die stacking;
DRAM;
caches;
memory;
servers;
73.
A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events
机译:
用于测量攻击者的侧通道信号的实用方法,用于指令级事件
作者:
Callan Robert
;
Zajic Alenka
;
Prvulovic Milos
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cryptography;
decision making;
program processors;
SAVAT;
decision-making;
electromagnetic emanation measurement;
instruction-level events;
laptop systems;
measurement equipment;
off-chip memory accesses;
on-chip instructions;
processor architecture;
program execution;
side channel vulnerability;
side-channel signal available to attacker;
single-instruction difference;
Area measurement;
Frequency measurement;
Instruments;
Measurement errors;
Measurement uncertainty;
Time measurement;
EM emanations;
computer security;
measurements;
metrics;
side channel;
vulnerability assessment;
74.
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors
机译:
使用ECC反馈将导电在低压处理器中的电压炒作
作者:
Bacha Anys
;
Teodorescu Remus
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
energy conservation;
error correction codes;
power aware computing;
reliability;
ECC feedback;
ECC-protected cache lines;
Intel Itanium processor;
Itanium-based server;
energy savings;
energy-efficient solution;
error correcting code;
hardware mechanism;
low-voltage computing;
low-voltage operation;
low-voltage processors;
power-constrained environments;
reliability challenges;
safety guard bands;
voltage margin reduction;
voltage noise;
voltage speculation;
Error analysis;
Error correction codes;
Hardware;
Low voltage;
Monitoring;
Program processors;
Timing;
75.
DaDianNao: A Machine-Learning Supercomputer
机译:
Dadiannao:一台机器学习超级计算机
作者:
Yunji Chen
;
Tao Luo
;
Shaoli Liu
;
Shijin Zhang
;
Liqiang He
;
Jia Wang
;
Ling Li
;
Tianshi Chen
;
Zhiwei Xu
;
Ninghui Sun
;
Temam Olivier
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
learning (artificial intelligence);
mainframes;
neural nets;
parallel machines;
CNN-DNN algorithmic characteristics;
DaDianNao;
GPU;
computational capacity-area ratio;
computational units;
convolutional neural network;
custom storage;
deep neural network;
general-purpose workloads;
high-degree parallelism;
industry-grade interconnects;
machine-learning supercomputer;
multichip machine-learning architecture;
multichip system;
neural network accelerators;
Bandwidth;
Biological neural networks;
Computer architecture;
Graphics processing units;
Hardware;
Kernel;
Neurons;
accelerator;
computer architecture;
machine learning;
neural network;
76.
Wormhole: Wisely Predicting Multidimensional Branches
机译:
虫洞:明智地预测多维分支
作者:
Albericio Jorge
;
San Miguel Joshua
;
Jerger Natalie Enright
;
Moshovos Andreas
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
energy conservation;
program compilers;
program control structures;
ISL-TAGE;
MPKI;
TAGE predictor;
energy efficiency;
global history fragments;
high-performance processors;
linear history based branch prediction strategies;
multidimensional branch prediction;
multidimensional correlations;
nested loops;
outer loop iterations;
power-constrained computing;
wormhole;
Accuracy;
Correlation;
Hardware;
History;
Indexes;
Radiation detectors;
Vectors;
Branch prediction;
instruction pipeline;
77.
COMP: Compiler Optimizations for Manycore Processors
机译:
COMP:编译器优化用于多核处理器
作者:
Linhai Song
;
Min Feng
;
Ravi Nishkam
;
Yi Yang
;
Chakradhar Srimat
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
data structures;
optimising compilers;
shared memory systems;
source code (software);
storage management;
compiler optimization for manycore processors;
data streaming;
data transfer overhead hiding;
memory access patterns;
memory usage minimization;
multicore processors;
offloaded codes;
pointer-based data structures;
shared memory mechanism;
source-to-source compiler optimizations;
vectorization;
Benchmark testing;
Coprocessors;
Data transfer;
Microwave integrated circuits;
Multicore processing;
Optimization;
Program processors;
Intel MIC;
compiler optimizations;
manycore coprocessors;
offload;
78.
Loop-Aware Memory Prefetching Using Code Block Working Sets
机译:
使用代码块工作集预取的循环感知内存预取
作者:
Fuchs Adi
;
Mannor Shie
;
Weiser Uri
;
Etsion Yoav
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
iterative methods;
performance evaluation;
storage management;
CBWS prefetcher;
PARSEC suites;
Parboil suites;
SMS prefetcher;
SPEC CPU2006 suites;
SPLASH suites;
access pattern;
code block recurring;
code block working set prefetcher;
code block working sets;
data prefetching;
loop iterations;
loop-aware memory prefetching;
memory instructions;
memory prefetchers;
spatial memory streaming prefetcher;
static instruction;
tight loop iterations;
trigger instruction;
Benchmark testing;
Hardware;
History;
Prefetching;
Runtime;
Tracking loops;
Vectors;
CBWS;
Cache;
Differentials;
Loops;
Prefetching;
79.
Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated Systems
机译:
微切片虚拟处理器隐藏统一系统不连续CPU可用性的影响
作者:
Jeongseob Ahn
;
Chang Hyun Park
;
Jaehyuk Huh
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
cache storage;
microprocessor chips;
operating systems (computers);
scheduling;
ubiquitous computing;
virtual machines;
virtualisation;
CPU resources;
CPU virtualization;
coarse-grained time sharing techniques;
coarse-grained time slices;
consolidated systems;
context switching overheads;
discontinuous CPU availability;
hypervisors;
interrupt handling;
lock handling;
low-cost context-aware cache insertion policies;
microsliced virtual processors;
operating systems;
physical core time-sharing;
scheduling latencies;
system virtualization proliferation;
time-sharing CPUs;
virtual CPUs;
virtual machines;
virtual time discontinuity problem;
Context;
Kernel;
Prefetching;
Switches;
Throughput;
Virtual machine monitors;
context prefetch;
context preservation;
virtual time discontinuity;
virtualization;
80.
Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution
机译:
ISO-X:用于硬件管理孤立的执行的灵活架构
作者:
Evtyushkin Dmitry
;
Elwell Jesse
;
Ozsoy Meltem
;
Ponomarev Dmitry
;
Abu Ghazaleh Nael
;
Riley Ryan
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
security of data;
storage management;
trusted computing;
FPGA;
ISA instructions;
Iso-X;
fine-grained hardware-supported framework;
fine-grained isolation;
flexible architecture;
flexible memory allocation;
hardware-managed isolated execution;
hardware-only trusted computing base;
isolated execution;
low-complexity;
memory-page level;
operating system;
run-time performance overhead;
Hardware;
Memory management;
Program processors;
Security;
Virtual machine monitors;
isolated execution;
security;
81.
Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures
机译:
城堡:高效保护堆叠的存储器从大粒度故障
作者:
Nair Prashant J.
;
Roberts David /A/.
;
Qureshi Moinuddin K.
会议名称:
《IEEE/ACM International Symposium on Microarchitecture》
|
2014年
关键词:
DRAM chips;
cache storage;
parallel memories;
3DP;
Chip Kill-like ECC codes;
Citadel;
DDS;
DRAM failures;
TSV-Swap;
bank failures;
bank granularity;
cache line;
column failure;
data-striping;
dynamic dual granularity sparing;
faulty address-TSV;
faulty data-TSV;
large-granularity failures;
memory architecture;
memory failure;
memory level parallelism;
row failures;
row granularity;
stacked memory design;
stacked memory modules;
stacked memory protection;
symbol-based codes;
through-silicon via;
tri dimensional parity;
Circuit faults;
DRAM chips;
Error correction codes;
Reliability;
Three-dimensional displays;
Through-silicon vias;
DRAM;
Error Correcting Code;
Faults;
Resilience;
Stacked Memory;
Through Silicon Vias;
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