Fast floorplanning for effective prediction and construction

摘要

Floorplanning is a crucial phase in VLSI physical design. Thensubsequent placement and routing of the cells/modules are coupled verynclosely with the quality of the floorplan. A widely used technique fornfloorplanning is simulated annealing. It gives very good floorplanningnresults but has major limitation in terms of run time. For circuit sizesnexceeding tens of modules simulated annealing is not practical.nFloorplanning forms the core of many synthesis applications. Designersnneed faster prediction of system metrics to quickly evaluate the effectsnof design changes. Early prediction of metrics is imperative fornestimating timing and routability. In this work we propose anconstructive technique for predicting floorplan metrics. We show how tonmodify the existing top-down partitioning-based floorplanning to obtainna fast and accurate floorplan prediction. The prediction gets better asnthe number of modules and flexibility in the shapes increase. We alsonexplore applicability of the traditional sizing theorem when combiningntwo modules based on their sizes and interconnecting wirelength.nExperimental results show that our prediction algorithm can predict thenarea/length cost function normally within 5-10% of the results obtainednby simulated annealing and is, on average, 1000 times faster