Sub-100nm technologies drive single-wafer wet cleaning

摘要

The stringent requirements of sub-100nm technologies tare pushing the need for single-wafer cleaning methods. As device dimensions shrink, the size of killer defects also decreases, requiring economical and environmentally friendly cleaning processes with increased particle removal efficiency. This article proposes a single-wafer, single-chemistry cleaning system with optimized megasonics and a drying method that leaves the wafer watermark-free. Cleaning processes are a fundamental step in the production of micro-electronic prod-ucts. Because of inherently small geome-tries, metallic contamination on the wafers can seriously degrade device performance. Cal-cium and iron have been identified as the most detrimental metals, associated with gate oxide integrity (GOI) degradation. Now with shrinking of gate dimensions, the size of "killer defects" will reach the nanometer scale ― 50nm for the 100 nm technology node. In order to meet the stringent gate-oxide defect density requirements of the future, cleaning strategies with a higher performance have to be developed. To make them production-worthy, cost and environmental issues must also be addressed.