A perspective on enhancing mobilities

摘要

Key metrics for enhanced MOSFET per-formance are increased speed, increased drain current at saturation (I_(dsat), and reduced capacitance equivalent thickness (CET) in inversion. The maximum attainable I_(dsat) for silicon MOS-FETs has been noted to be limited by the thermal injection of carriers from the source into the channel, with Ge suggested as a more efficient injecting material than Si (M. Lund-strom*). Nevertheless, it is advantageous to enhance the carrier mobility beyond the universal mobility curves to achieve future speed and I_(dsat) device metric goals, as was extensively discussed at the 2003 IEDM. Inducing a tensile strain in the channel can enhance both the electron and hole mobility beyond the universal mobility curves. For optimal CMOS performance, it is desirable to increase the hole mobility more than the electron mobility so that the final, enhanced values of the two mobilities are more equal than for unstrained silicon. Numerous techniques have been shown to induce strain in the channel including the influence of a tensile (localized) film above the channel (A. Shimizu et al. and K. Ota et al.), shallow trench isolation (STI) induced stresses (Y.G. Wang et al.) as well as the role of the source/drain silicide (A. Steegen).