Cell chip designed for ease of manufacture

摘要

While the new IBM-Sony-Toshiba mul-tiprocessor Cell chip takes a radically new approach to design to get its blazing 4GHz, 256 gigaflops performance with relatively low power consumption (around 48W), it opts for some relatively conservative process technology to ramp up as quickly as possible to volume production. For the most bang for the buck from new technologies, developers put their emphasis on design-for-manufacturability (DFM), SOI, and strained silicon. So the first version will be 90nm, not 65nm, given the issues of getting yields for the large 221mm~2 chip, roughly twice the size of the Pentium Prescott. The exotic raised transistor structures and more extreme spun-on low-k dielectrics originally considered were dropped along the way in favor of processes already up and working. Both the 90nm and the 65nm version will use CVD SiOC, with a k value of about 3.