Getting the most function out of the least chip area has been the main goal of IC designers since the beginning of the industry. Their creativity gave rise to complex 2D layouts that were shrunk geometrically one generation after another until about the 90nm node. At that point, the fact that the circuit features had become so much smaller than the exposure wavelength made imaging problematic. Circuit variability increased and lithography hotspots appeared at corners, isolated contacts and other structures, limiting yield. Attempts to restrict designer creativity to manufacturable shapes through restrictive design rules had only limited success. Now, Campbell, CA-based startup Tela Innovations proposes a radical step to solve the industry's layout problems by employing only certain pre-defined linear topologies. Previous proposals to limit design flexibility in that way had been rejected because of the fear of increased circuit area and the cost of redesigning entire cell libraries.
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