It's springtime for creative engineers

摘要

It's springtime for engineers in electronics, computing, and chip architecture. That was the message of a stimulating talk by Paolo Gargini, Intel Fellow and guiding light for the International Technology Roadmap for Semiconductors, at the last SEMICON West. He pointed out that since the early 1970s, performance improvement for every new chip generation was a side benefit of following shrink rules set up for IC transistors by IBM's Robert Dennard in 1973. Chip designers got faster circuits for free! Sadly, we all eventually learned that there is no such thing as a free lunch. As conductors got narrower, resistivity mounted. As they were crammed closer together, capaci- tance increased. A higher RC time constant slowed circuits. Copper helped for awhile, but it has taken longer to figure out how to do low-κ dielectrics for lowering capacitance. Meanwhile, the gate dielectric got too thin, raising leakage Current, and short channel effects set in as the gate length shrunk. It has been tough to find good high-κ dielectric/metal gate combinations to get a thicker effective oxide thickness and to eliminate the polysilicon depletion layer problem.