Brion powers up to meet DPT challenges at 32nm-22nm

摘要

At the opening of the SPIE Advanced Lithography Symposium, Brion Technologies unveiled a more powerful version of its Tachyon Computational Lithography platform and the release ofTachyon DPT, software that allows chipmakers to meet the low k_1 requirements for memory and logic devices at 32nm and below. Neal Callan, VP of product operations at Brion, described for SST the four key elements of the new Tachyon 2.5 hardware platform: 1) an upgraded CPU from dual-core to a quad-core; 2) faster aerial image computations; 3) moving more compute-intensive operations from the CPU onto the FPGA, which is also fester than in the previous generation; and 4) improved system-level communication and data-flow optimization.