Synopsys' new DFM strategy: Focus on in-design verification

摘要

With the release of its IC Validator targeting sub-45nm designs, Synopsys Inc. is inaugurating a new strategy with respect to DFM, to differentiate what it considers manufacturing software from the "true DFM" tools on the design side of the equation.rnThe IC Validator DRC/LVS for in-design physical verification and signofffor advanced designs at 45nm and below aims to reduce total physical verification time by using in-design verification, stream-out reduction, incremental processing, automatic error detection and fixing, and near-linear scalability across multiple CPU cores.