Learning the secrets of design for yeild

摘要

Random process variations and layout-dependent effects are a fact of life for designers working at the more advanced process nodes and become critical at 45nm. Besides random and systematic variation effects, reliability effects, such as bias-temperature-instability (BTI), also become prevalent, introducing another dimension of variations that impact parametric yield. These variations are unavoidable and, in fact, increasing as we move to more advanced nodes, where circuit designers encounter yield problems and need to spend extra effort on variation analysis for yield and performance trade-off.