Nanoscale CMOS: potential nonclassical technologies versus a hypothetical bulk-silicon technology

摘要

Using our process/physics-based compact models (UFDG and UFPDB) in Spice3, we project device characteristics and CMOS performances of nonclassical UTB (FD/SOI and DG) and classical, hypothetical bulk-Si technologies optimized at the L_g = 28 nm node. For the nonclassical MOSFETs (generally with metal gates for V_t control) with the same UTB thickness (t_(Si)), the DG devices are shown to be far superior for SCE control. Also, with regard to speed, the DG devices are generally superior to the FD/SG counterparts because of higher drive currents. However, for light loads and moderate supply voltages, a suboptimal FD/SG design (with the same t_(Si) for both LOP and HP CMOS applications is found to yield speeds comparable to the DG designs, even though its current drive is much lower and its SCEs are much more severe. This surprising result is explained by the much lower FD/SG intrinsic gate capacitance, C_G(V_(GS))- When the FD/SG CMOS design is optimized by aggressive scaling of the UTB thickness, its high-V_(DD) speed diminishes (but is still comparable to that of DG CMOS) because of higher C_G at intermediate gate voltages, while its low-V_(DD) speed improves due to increased current. Compared to these nonclassical CMOS designs, the delay of the classical bulk-Si/ SG CMOS is predicted to be much longer due mainly to its high C_G in the weak/moderate inversion region and relatively low drive current. Finally, we show how FD/SOI CMOS speed is degraded as the BOX is thinned, thereby suggesting that such thinning is not a good design tradeoff.