Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution

摘要

This work proposes a planar fully depleted "folded" technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Noth-ing) process, to provide ultra thin body and buried oxide (UTB~2) devices with improved drive current I_(on) for a given designed footprint W_(design) when scaling the device width. We compare the fabrication and electrical behavior between (110) channel, i.e. 0°-rotated wafer, and (100) channel, i.e. 45°-rotated wafer, for the same (100) surface orientation.