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Highly Controllable Dual-Gate Microcrystalline Silicon Thin Film Transistor Processed At Low Temperature (T< 180 °C)

机译:低温(T <180°C)处理的高度可控的双栅极微晶硅薄膜晶体管

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摘要

The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180 °C, is shown to lead to a very efficient control of the threshold voltage VTH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of VTH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50 nm thick, active layer and to its electrical quality that leads to a full depletion.
机译:将顶栅添加到在最高温度为180°C的底栅微晶硅薄膜晶体管(TFT)中进行添加,可以非常有效地控制阈值电压VTH。这样就可以实时控制CMOS配对。 VTH的变化与顶栅控制的电压的变化之比即耦合系数的值为0.7。这种有效的控制主要是由于使用了非常薄的50 nm厚的有源层,并且其电气质量导致完全耗尽。

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  • 来源
    《Solid-State Electronics》 |2011年第1期|p.140-144|共5页
  • 作者单位

    Institute of Electronics and Telecommunications ofRennes, IETR. University ofRennes I, Bat. 11B, Campus de Beaulieu, 35042 Rennes Cedex, France;

    Institute of Electronics and Telecommunications ofRennes, IETR. University ofRennes I, Bat. 11B, Campus de Beaulieu, 35042 Rennes Cedex, France;

    Institute of Electronics and Telecommunications ofRennes, IETR. University ofRennes I, Bat. 11B, Campus de Beaulieu, 35042 Rennes Cedex, France;

    Institute of Electronics and Telecommunications ofRennes, IETR. University ofRennes I, Bat. 11B, Campus de Beaulieu, 35042 Rennes Cedex, France;

    Institute of Electronics and Telecommunications ofRennes, IETR. University ofRennes I, Bat. 11B, Campus de Beaulieu, 35042 Rennes Cedex, France;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    CMOS electronics; Low temperature substrate; Microcrystalline silicon; DG-TFT;

    机译:CMOS电子器件;低温基板;微晶硅;DG-TFT;

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