Investigation of scalability of Ino.7Gao.3As quantum well field effect transistor (QWFET) architecture for logic applications

摘要

In this paper, the scalability of In_(0.7)Ga_(0.3)As QWFET is investigated using two-dimensional numerical drift-diffusion simulation. Numerical drift-diffusion simulations were calibrated using experimental results on short-channel lno.7Gao.3As QWFETs [7] to include the effects of velocity overshoot. Logic figures of merit (sub-threshold slope, saturated threshold voltage, drain induced barrier lowering, I_(ON)/I_(OFF) ratio over a specified gate swing, effective injection velocity and intrinsic switching delay) extracted from the numerical simulations are in excellent agreement with the experimental data. Three alternate QWFET device architectures are proposed and thoroughly investigated for 15 nm node and beyond logic applications. Amongst them, double-gate Ino.7Gao.3As QWFET shows the best scalability in terms of logic figures of merit, thus making it an ideal candidate for the design and demonstration of the ultimate scaled transistor.