A high performance 0.35-/spl mu/m 3.3-V BiCMOS technology optimized for product porting from a 0.6-/spl mu/m 3.3-V BiCMOS technology

摘要

A 0.35-/spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-/spl mu/m 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-/spl mu/m 3.3-V BiCMOS design to a 0.35-/spl mu/m design is described. The silicon results are described.