A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation

摘要

Many cost-aware IoE devices require embedded nonvolatile memory (eNVM) to achieve high-speed read and low-power write operations for serving as code and data storage unit. Resistive random access memory (ReRAM) is a good candidate for eNVM of Internet-of-Everything (IoE) but suffers low read yield and require long read latency (T-CD) against small R-ratio, large cell-resistance variations, and device-mismatch induced input offset at current-mode sense amplifier (CSA). The wide distribution in write time also causes large wasted write power (E-W) and long NVM-stress-time (T-STRS). This paper proposes a bitline-current-aware small-offset CSA, using dynamic trip-point-mismatch sampling (DTPMS) scheme, to improve read yield and shorten T-CD. This paper also proposes a low dccurrent voltage-mode write termination (LDC-VWT) module, including SET and RESET termination circuits, to suppress E-W and T-STRS. A fabricated 65-nm 2-Mb ReRAM macro achieved T-CD = 2.6 ns and confirm the write-termination operations for reduction in T-STRS and E-W.