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机译:使用32.768kHz参考时钟和≤0.45-V电源的蓝牙低功耗全数字PLL
Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan;
Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan;
Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan;
Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan;
Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan;
School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, Ireland;
Phase locked loops; Radio frequency; Oscillators; Clocks; Bluetooth; Transceivers; FinFETs;
机译:全数字自适应时钟,可承受低压运行中的瞬态电源噪声
机译:适用于蓝牙LE的0.5V 1.6mW 2.4GHz小数N全数字PLL,具有在28nm CMOS中使用开关电容倍增器的PVT不敏感TDC
机译:用于扩展频谱时钟发生器(SSCG)的6 GHz全数字锁相环
机译:采用16nm FinFET的0.45V亚兆瓦全数字PLL,用于蓝牙低功耗(BLE)调制和使用32.768kHz参考的瞬时通道跳变
机译:用于时钟发生器的低抖动PLL,具有使用DC-DC电容转换器的对电源噪声不敏感的VCO。
机译:通过唤醒无线电使能量收集无限度的电气设备的低延迟蓝牙低能量
机译:在同步的全数字PLL网络中生成时钟信号
机译:采用10单元库的全数字基带65nm pLL / FpLL时钟倍频器。