A planar asymmetric Schottky barrier source/drain structure for nano-scale MOSFETs

摘要

An n-channel planar asymmetric Schottky barrier source/drain MOSFET (ASB), in which the source-side Schottky barrier is higher (0.9 eV, for PtSi) and the drain-side one is lower (0.2 eV, for ErSi), has been investigated. A fabrication proposal for nano-scale ASB devices has been put forward based on the spacer technique. This method is compatible with conventional CMOS processing. The characteristics of a 28 nm gate-length ASB device have been simulated with a numerical simulator, and the data are compared with the simulated results of corresponding conventional Schottky barrier MOSFETs. Comparison results have demonstrated that the ASB structure can efficiently suppress the leakage current and the I-on/I-off ratio can be much improved.