Higher Yields With Trench-First BEOL

摘要

In back-end-of-line (BEOL) processing, important changes include the replacement of low-k dielectrics with ultralow-k dielectrics and the non-linear increase of copper resistivity with sub-100 nm scaling of interconnect dimensions. In a recent paper presented at the International Electron Devices Meeting (IEDM), the Crolles, France-based joint venture between STMicroelectronics, Freescale Semiconductor and Philips Semiconductors demonstrated a fully integrated 300 mm, 65 nm BEOL that employed a trench first with hard mask (TFHM) dual-damascene approach. This strategy allows faster yield ramp because of better compatibility with low-k materials and improved lithography process window. The group was able to reduce the time-to-yield performance from 18 months to 7 months between the 90 and 65 nm nodes. In a second paper by Philips Semiconductors, STMicroelectronics and CEA LETI (Grenoble, France), the group showed that ALD barriers of TaN demonstrate better RC delay and reliability behavior than PVD TaN in the sub-100 nm regime.