TAP Trends Push Greater Functionality

摘要

Wafer-level packaging (WLP), system-in-package (SiP), three-dimensional integration and the challenge of lead-free processing are presently driving the state-of-the-art in assembly and packaging. In test, the challenge is to keep up with ever-faster chips with increasingly diverse functionality and higher pin counts. From a sheer volume perspective — looking at all the ICs produced in the world today — the vast majority is still packaged with what is now fairly traditional packaging technology: The die is bonded onto a leadframe, connected to the leadframe by wire bonding, and then encapsulated in a black epoxy. But the excitement (and explosive growth) is really in the leading-edge high-density, high-pin-count devices that are pushing the development of more sophisticated types of packaging, most notably flip-chip packages, which are now approaching 10% of the overall market.