Yield Learning Flowprovides Faster Production Ramp

摘要

When designing and manufacturing ICs at ≤65 nm, the interaction of process variation and design features create systematic defects that result in yield problems. Traditional yield-management approaches are proving to be less effective for identifying these problems because of time and equipment limitations and limited access to, or usefulness of, manufacturing process data. At today's technology nodes, the traditional failure dataset simply is unable to identify all the yield limkers. Under increasingly competitive market pressures, IC companies need a new process and new tools to better manage yield ramp and boost their mature yields. Not only is analyzing diagnosis results in volume called for, but we also need detailed diagnosis of scan-feature failures that is layout-aware. The evolution of this process is a statistical analysis tool that visualizes, drills down and identifies observable and hidden yield-limiting defects with greater accuracy and more quickly than has ever been done before.