XSG-based HLS flow for optimized signal processing designs for FPGAs

摘要

This paper proposes an XSG(Xilinx System Generator) based HLS (High level synthesis) flow for FPGAs. The tool includes an operation classification process and a formal clustering technique for an optimized allocation phase. During the binding step, a new target based resource sharing strategy is proposed. We demonstrate the effectiveness of the proposed tool against the direct implementation using both Xilinx System Generator, Vivado HLS, Legup and (Ronak and Fahmy, 2016 [1]) on several benchmarks from the signal processing domain. The results show significant improvements. The power consumption enhancement reached 79% in comparison with the direct implementation, 50% in comparison with the Vivado HLS implementation and 70% in comparison with (Ronak and Fahmy, 2016 [1]). The area improvement attained 85% in comparison with the direct implementation, 90% in comparison with the Vivado HLS implementation, 88% in comparison with Legup and 82% in comparison with (Ronak and Fahmy, 2016 [1]). (C) 2019 Elsevier B.V. All rights reserved.