...
机译:sub-V_T域中65 nm双VV CMOS中数字抽取滤波器的超低功耗设计探索
Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00 Lund, Sweden;
Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00 Lund, Sweden;
Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00 Lund, Sweden;
Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00 Lund, Sweden;
Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00 Lund, Sweden;
Energy dissipation; Ultra low power; Decimation filters; Half hand filters; 65 nm; Suh'threshold; CMOS; Unfolding; Wireless devices; Implantable devices;
机译:65/45 nm CMOS时序约束下的鲁棒且节能高效的超低压电路设计
机译:超低电压,低噪声,高线性度900MHz接收器,具有在65nm CMOS中进行数字校准的带内前馈干扰消除功能
机译:基于9位电阻的高数字温度传感器,带有SAR量化嵌入式差分低通滤波器,采用65nm CMOS和2.5-
机译:65nm子V_T CMOS数字抽取滤波链的设计探索
机译:CMOS抽取和内插半带FIR数字滤波器的设计和VLSI实现。
机译:用于数字域CMOS TDI图像传感器的低功耗数字累加技术
机译:65/45 nm CmOs时序约束下的鲁棒节能超低电压电路设计