Wafer mapping of ESD performance

摘要

This paper reports, for the first time, on a variation of the ESD performance of CMOS ICs acorss the wafer. A variation of the TLM-ESD failure threshold by as much as a factor of 4(four) was found within a single wafer. Comparable results were found for HBM-ESD test. Implications of this finding for process control and ESD qualification are discrussed. As main conclusion, ESD wafer mapping for process adn IO library qualification is proposed.