The semiconductor industry is heading for a train wreck, warns John Petersen. The cause? Systematic failures "where the design and the process have a mismatch." The result? Yield hits and idle lines caused by processes running at much less than their full potential. Petersen, a former fellow at International Sematech, asserts that the bulk of these mismatches occur in lithography. He acknowledges the industry is debating the extent that problems can be traced to lithography, or to the interaction of lithography and layers. What is certain, though, is that the yield issues have become particularly acute at the sub-180-nm technology node, where interconnect wiring, structure, and gate uniformity contribute to performance problems, Petersen says.
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