Emerging trends in ultra-miniaturized CMOS (Complementary metal-oxide- semiconductor) transistors, single-electron and molecular-scale devices: A comparative analysis for high-performance computational nanoelectronics

摘要

The current status and trends of the three ultra-small scale integrated circuit technologies, namely nanoscale CMOS, single- and molecular electronics are comprehensively reviewed. A comparative study is made, pointing out their relative pros and cons for nanoelectronic computing. Crucial aspects of MOS downscaling include, from the physical viewpoint, the infamous short-channel effect caused by drain induced barrier lowering (DIBL), the narrow width effect associated with small channel width, the combined small-geometry effect, and hot-carrier degradation; together with the conflicting requirements of shallow silicided junctions and low junction leakage; random doping fluctuations; ultrathin gate oxide reliability; polysilicon depletion effect; atomic scale roughness at the Si/SiO_2 interface; and high lithographic expenses, on the technological side. For sustaining growth in device density, a possible route for the microelectronics industry is to shift from the traditional field-effect transistor-based paradigm to one based on nanostructures. Single electronics has not been able to bear the envisaged fruits. While prospects of solo single-electron logic are murky, the concept of a mixed single-electron device/FET multi-valued logic and memory appears to be beneficial. But to achieve the ultimate performance, it may be expedient to transform our philosophy fundamentally to start from the molecular level, instead of scaling down old technologies to nanometer level. Molecular electronics appears to be the appropriate approach because the development cost of scaled technologies, and cost-effectiveness of resulting devices is not encouraging. The review seeks to provoke keen interest in these futuristic nanotechnologies.