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Multiple modular very long instruction word processors based on field programmable gate arrays

机译:基于现场可编程门阵列的多个模块化超长指令字处理器

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摘要

Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M~3) approach. Our goals are to keep the flexibility of DSP in order to shorten the development cycle and to use the totality of the powerful FPGA resources in order to increase real-time performance. Some common algorithms of image processing and a face tracking in video sequences application were created and validated on an FPGA VirtexII-2000 multimedia board using the development cycle proposed. Our results demonstrate that an algorithm can easily be, in an optimal manner, specified and then automatically converted to VHDL language and implemented on an FPGA device with system-level software. This makes our approach suitable for developing co-design environments. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability. In this paper, the target VLIW processor is the DSP TMS320C6x. Nonetheless, our design cycle can be generalized to other DSPrnprocessors.
机译:具有巨大存储容量和可重新配置潜力的现代现场可编程门阵列(FPGA)芯片为嵌入式系统的快速原型开发开辟了新的领域。随着高密度FPGA的出现,现在可以在FPGA中实现高性能的超长指令字(VLIW)处理器内核。本文介绍了有关通过利用FPGA技术为实时图像处理应用启用DSP TMS320 C6201模型的研究结果。我们提出了带有可变指令集的模块化DSP C6201 VHDL模型。我们将此新开发称为最低强制性模块(M〜3)方法。我们的目标是保持DSP的灵活性,以缩短开发周期,并使用全部强大的FPGA资源,以提高实时性能。使用提出的开发周期,在FPGA VirtexII-2000多媒体板上创建并验证了一些常见的图像处理算法和视频序列应用中的面部跟踪算法,并对其进行了验证。我们的结果表明,可以轻松地以最佳方式指定算法,然后将其自动转换为VHDL语言,并使用系统级软件在FPGA器件上实现。这使我们的方法适合于开发协同设计环境。我们的方法对协同设计工具应用了一些标准:灵活性,模块化,性能和可重用性。本文中的目标VLIW处理器是DSP TMS320C6x。但是,我们的设计周期可以推广到其他DSPrn处理器。

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