A Metallic CNT Tolerant Design Methodology for Carbon Nanotube-Based Programmable Gate Arrays

摘要

Carbon nanotube field effect transistor (CNFET) is one of the promising technologies as a replacement for current CMOS technology due to its excellent electronic properties. CNFETs can be fabricated in regular structures, making them ideal for creating the repetitive architectures found in field programmable gate arrays (FPGAs). However, CNFETs face some fabrication challenges. The unwanted metallic carbon nanotubes (CNTs) are one of the major challenges in using CNFET technology for FPGAs. In this paper, we take the advantage of FPGAs programmability allowing reconfiguration around the metallic CNTs to tolerate this defect. We demonstrate a multi-stage solution to the metallic CNT problem in CNFET-based FPGAs that does not require any metallic nanotube removal of any kind. The proposed methodology consists of four consecutive stages in logic mapping process: (i) reordering of input variables, (ii) inputs complementing, (iii) adding inputs redundancy to basic logic element (BLE) and (iv) BLE lookup table (LUT) splitting. A fault simulation tool is designed to work closely with VPR, an academic FPGA CAD tool, to provide the investigation of metallic CNTs effects on CNFET-based FPGAs. Experimental results show that the proposed method can successfully map all logical nets at a cost of 4.5x area overhead if the fraction of metallic CNTs is reduced to 30%.