SOLDER JOINT RELIABILITY ANALYSIS OF A WAFER-LEVEL CSP ASSEMBLY WITH CU STUDS FORMED ON SOLDER PADS

摘要

This work attempts to enhance solder joint reliability under thermal cycle loading by introducing Cu studs to the solder joints of wafer-level chip size packaging (WLCSP). The 3-D nonlinear finite element method is adopted to simulate the thermal induced stress / strain responses of solder joints with Cu studs on the surfaces of solder pads. To accurately predict the thermal fatigue life of solder joints, their reflow geometry is calculated using the Surface Evolver. This investigation also explores the effects of various parameters including the Cu stud's dimension, shape, material properties and the die and PCB thicknesses on solder joint reliability. To demonstrate the accuracy of the finite element models, the analytical results were compared with the experimental results and the experimental data reported in the literature. The analytical results establish that solder joint reliability can be significantly improved by introducing large Cu studs to solder joints and can be further enhanced by combining large Cu studs with thin die or PCB.