Negative capacitance in optically sensitive metal-insulator-semiconductor-metal structures

摘要

We report a strong negative capacitance effect in back to back combination of a metal-insulator-semiconductor (MIS) structure and a metal-semiconductor junction, which is fabricated on an n type Silicon-on-Insulator substrate. The MIS capacitor comprises a SiO_2-HfO_2 insulator stack with embedded Pt nanoparticles. The capacitor undergoes a voltage stress process and thereby turns into a varactor and a photodetector. The negative capacitance is observed only under illumination in structures that employ a Schottky back contact. A symmetric double or an asymmetric single negative capacitance peak is observed depending on the nature of illumination. The phenomenon is attributed to the modulation of the semiconductor conductance due to photo generated carriers and their incorporation in trapping/de-trapping processes on interfacial and post filamentation induced defects in the insulator stack. The frequency range of the observed effect is limited to 100 kHz. Large ratios of light to dark and maximum to minimum of negative capacitances as well as of the obtained sensitivity to the applied voltage are, respectively, 105, more than 100, and 10-15. These were measured at 10kHz under illumination at 365 nm with a power of 2.5 × 10~(-6) W.