Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistors by a Novel Direct Current Current-Voltage Technique

摘要

Shallow trench isolation (STI) based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. A novel direct current current-voltage (DCIV) technique demonstrated with multiple sharp peak signals is proposed to characterize interface state generation in the channel and in the STI drift regions separately. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by proposed technique. A two-dimensional numerical device simulation is performed to obtain insight into the proposed technique and device degradation characteristics under hot-carrier stress conditions. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our results show that the maximum /sub stress becomes the worst hot-carrier degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.