A hybrid space vector modulation for the near-zero common-mode voltage and common-mode current mitigation in diode-clamped multilevel-inverter-fed induction motor drive

摘要

Three-level diode-clamped (DC) multilevel inverters (MLIs) and its pulse width modulations (PWMs) are studied widely due to its extensive rewards in industrial drives. These modulation schemes are mainly concentrated to mitigate the zero common-mode (CM) voltage (CMV) and CM current (CMC). Unfortunately, although achieving near-zero CMV, these conventional methods are inadequate to maintain the DC-link low-frequency neutral point voltage oscillations. Hence, bulky DC-link capacitors are used in DC-MLIs. In this article, a full CM voltage eliminated the modified space vector modulation (SVM) method by combining the three medium switching vectors ((MV)-V-3) with one zero vector and two medium switching vectors (M(2)ZV) is proposed. The hybridization of (MV)-V-3 + M(2)ZV uses the simple digital circuit to combine (MV)-V-3 and M(2)ZV, which creates near-zero CMV and CMC with an improved DC-link capacitor voltage balancing. The studies on the creation and effects of CMV and CMC are presented in detailed. Compared with the early reported full CMV elimination research works, the proposed method maintains the DC-link capacitors voltage balancing without compromising the complete elimination of the CMV. Depending on the reference vector modulation indices and DC-link capacitor voltages, the proposed method uses the mixture of both the (MV)-V-3 and M(2)ZV switching states. The nominated switching vectors keep the CMV and CMC near to zero with capacitor voltage fluctuation with 1.8%. The mathematical analysis of CMV and CMC, operating principles of (MV)-V-3 and M(2)ZV, and comparison of the proposed method with other reported methods are presented. The proposed hybrid SVM is compared with the other conventional SVM and multicarrier PWM control by MATLAB/Simulink simulations. Finally, laboratory-scale experimentations were developed with the support of Spartan-6 FPGA to test the conventional and proposed SVM method. The validated results confirmed the effectiveness of the proposed hybridization of (MV)-V-3 + M(2)ZV to maintain the zero CMV and DC-link balancing together.