Design and Implementation of an Embedded NIOS Ⅱ System for JPEG2000 Tier Ⅱ Encoding

摘要

This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research in this field centers on acceleration of the EBCOT Tier Ⅰ encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier Ⅱ processing as the back end of an encoding pipeline. The Altera NIOS Ⅱ processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix Ⅳ FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.