Design of self-biased folded cascode CMOS op-amp using PSO algorithm for low-power applications

摘要

Static power dissipation is one of the most important problems that impedes the progress of electronic circuits so it must be reduced. Complementary metal-oxide semiconductor (CMOS) op-amp using self-biased technique is designed and improved to be less consumption power. Moreover, particle swarm optimisation (PSO) algorithm is used in this article to deal with Static power dissipation. The use of PSO algorithm led to reduce static power dissipation of self-biased folded cascode CMOS op-amp from 0.86 to 0.485 mW keeping the efficiency of optimised op-amp. In addition, some of performance parameters are optimised too, such as voltage gain of operational amplifier (Av), unity gain bandwidth GB and reduction of the chip area. The PSPICE simulation results using 0.35 urn MIETECH CMOS technology shows that an open loop gain of the proposed CMOS op-amp of 82 dB based on PSO algorithm, while it produces 7953 dB without PSO algorithm and unity gain bandwidth is increased to 8.8 MHz with PSO compared with 6.72 MHz without PSO algorithm.