Design and Implementation of Area and Power Efficient Network on Chip on FPGA

摘要

As the number of on-chip cores increases, a scalable and high-bandwidth communication fabricto connect them becomes critically important. As a result, packet-switched on-chip networks are fast replacing buses and crossbars to emerge as the pervasive communication fabric in many-core chips. In this paper, a novel area and power efficient scalable network on chip architecture proposed on Spartan6 FPGA. The NoC was designed and prototyped with respect to simplicity and a small hardware footprint.