机译:用于自适应系统的可重构有限冲激响应滤波器的设计与实现
Department of Electronics and Communication Engineering, NSS College of Engineering, Palakkad, India;
Department of Electronics and Communication Engineering, Mar Baselios College of Engineering and Technology, Peermade, Idukki, India;
Department of Electronics and Communication Engineering, Sasurie College of Engineering, Vijayamangalam, Thirupur, India;
dynamic partial reconfiguration; dpr; field programmable gate array; fpga; fir filter; data path; fault detection; planahead;
机译:用于有限冲激响应滤波的分布式算法的可重构混合信号VLSI实现
机译:分布式算术的高性能可重构有限脉冲响应滤波器的分析与实现
机译:自适应有限脉冲响应滤波器的均衡实现约束
机译:可重构混合信号有限冲激响应滤波器的VLSI实现
机译:现场可编程门阵列上自适应有限冲激响应滤波器的高效架构。
机译:基于均匀的图案的区域高效和准确的随机计算有限脉冲响应滤波器
机译:可重构混合信号有限脉冲响应滤波器的VLsI实现