首页> 外文期刊>International journal of circuit theory and applications >A configurable 2-Gbps LVDS transceiver in 150-nm CMOS with pre-emphasis, equalization, and slew rate control
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A configurable 2-Gbps LVDS transceiver in 150-nm CMOS with pre-emphasis, equalization, and slew rate control

机译:具有150nm CMOS的可配置2Gbps LVDS收发器,具有预加重,均衡和转换速率控制

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A configurable full-duplex low-voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre-emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage-current-mode driver, which due to replica action, achieves a high-impedance current-mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band-limited pre-driver, while the pre-emphasis is achieved through a capacitive feed-forward. The receiver employs a large-input common-mode first stage enclosed in a common-mode control loop that enables its first stage to also act like a domain shifter (VDDIO-to-VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150-nm complementary metal-oxide-semiconductor, sharing the space with a larger die, occupying an area of 400 x 400 mu m. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4-in microstrip and a 10-m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built-in impedance calibrator minimizes the spread in the on-die termination at the near end provided by the transmitter-minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright (C) 2016 John Wiley & Sons, Ltd.
机译:提出了一种可配置的全双工低压差分信号收发器,该收发器可以配置用于较小的差分通道(几英寸的带状线)或较长的通道(10 m双绞线电缆)。可配置性以诸如预加重,均衡和转换速率控制之类的功能形式嵌入到收发器内。发射器采用混合电压-电流模式驱动器,由于复制动作,该驱动器实现了高阻抗电流模式信号分配,同时在近端提供了匹配的阻抗,以改善符号间干扰。发射机通过带限预驱动器实现压摆率控制,而预加重通过电容前馈实现。接收器采用封闭在共模控制环路中的大输入共模第一级,从而使它的第一级也可以像域移位器一样工作(VDDIO至VDDCORE),从而降低了总体功耗。接收器中的均衡是通过在接收器内部使用尺寸适当的有源感应负载来实现的。该收发器采用150 nm互补金属氧化物半导体设计和制造,与更大的裸片共享空间,占地400 x 400μm。测量结果表明,对于总长度为30 ps和180 ps的4英寸微带线和10 m双绞线CAT6电缆,收发器均以2 Gbps的速率工作。内置的阻抗校准器可将发射机提供的近端芯片上端接中的扩散降至最低,从而将整个过程,电压和温度拐角处的误码率降至最低。发送器以2 Gbps的速度运行时消耗的总功率为17 mW,即能量消耗为8.5 pJ /位;当以2 Gbps的速度驱动5 pF的负载时,接收器的总功耗为3.5 mW。版权所有(C)2016 John Wiley&Sons,Ltd.

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