A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation

摘要

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase-shifted circuit, and a carry chain is proposed. Dual-edge-triggered flip-flops are used in the phase-shifted circuit to generate signals with 45 degrees phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11-bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix-7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity whereR(2)is 0.99 and verify the effect of duty cycle compensation.