An efficient circuit for error reduction in logarithmic multiplication for filtering applications

摘要

Real-time digital signal and image processing applications, such as filtering, demand high performance. Often, multiplication is one of the most time-consuming steps of the filtering operation. Log-based multipliers have been used for improving multiplication efficiency at the expense of accuracy. The objective of the proposed work is to improve the accuracy of log-based hardware multipliers by appropriately altering the filter weights and without increasing the required resources.