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Wire density in CAE analysis of high pin-count IC packages: Simulation and verification

机译:高引脚数IC封装的CAE分析中的导线密度:仿真和验证

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Wire sweep has been recognized as one of the major defects in the encapsulation of microelectronic chips by the transfer molding process. As thinner and denser IC packages emerge, wire-sweep analysis becomes more challenging and troublesome. This paper studies the reactive flow in IC encapsulation by the CAE molding simulation and the wire-sweep phenomena. In fact, it presents a new methodology used to consider the effect of wire density (number of wire) by controlling the shape factor to simulate the flow resistance. The results show a better solution for melt-front advancement and wire-sweep prediction. Finally, one study case for high pin-count packages (BGA) is used to verify the research.
机译:扫线已被认为是通过传递模塑工艺封装微电子芯片的主要缺陷之一。随着更薄,更密集的IC封装的出现,扫线分析变得越来越具有挑战性和麻烦。本文通过CAE成型仿真和线扫现象研究了IC封装中的反应流。实际上,它提出了一种新方法,可通过控制形状因数来模拟流阻来考虑线密度(线数)的影响。结果显示了一种更好的解决方案,可用于熔体前移和线扫预测。最后,使用一个高引脚数封装(BGA)的研究案例来验证该研究。

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