Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Ceils at 45 nm

摘要

The quest for low power increases with the advancement in technology as a result of continuous device scaling. Static random access memory (SRAM) represents the technology workhorse due to its compatibility with the logic. Denser SRAM is required for modern high performance applications. The stability of SRAM in low power regime needs attention due to increasing effects of process variations in low dimensions. These variations are steep for the scaled devices. Data retention voltage (DRV) is the main parameter for SRAM to estimate the cell stability. This paper analyses the stability of SRAM in terms of process corner analysis of DRV. The process corner analysis in addition to temperature analysis is carried out with the Cadence Virtuoso tool using the 45 nm generic process design kit (GPDK) technology file. At lower temperature, the DRV is lowest at the FF process corner and highest at the SS corner. But for higher temperature, the highest value of DRV is obtained at the SF corner. Similarly, with varying cell ratio (CR), the process corner analysis shows that FF and TT are the best corners for low power operations.