机译:嵌入式处理器的高效泄漏指令TLB设计
The authors are with the Faculty of Science and Technology, Keio University, Yokohama-shi, 223-0061 Japan.;
The authors are with the Faculty of Science and Technology, Keio University, Yokohama-shi, 223-0061 Japan.;
The authors are with the Faculty of Science and Technology, Keio University, Yokohama-shi, 223-0061 Japan.;
The authors are with the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology, Koganei-shi, 184-8588 Japan;
The authors are with the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology, Koganei-shi, 184-8588 Japan;
The authors are with the Faculty of Science and Technology, Keio University, Yokohama-shi, 223-0061 Japan.;
leakage power; TLB; embedded processor;
机译:嵌入式处理器的高效泄漏指令TLB设计
机译:嵌入式处理器的高效泄漏指令TLB设计
机译:嵌入式处理器的高效泄漏数据TLB设计
机译:减少嵌入式处理器指令TLB的泄漏功耗
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机译:下一代嵌入式处理器中高度关联指令缓存的节能设计