机译:具有互连负载效应的CMOS栅极有效电容的非迭代计算方法
The authors are with the Graduate School of Production, In-formation and Systems, Waseda University, Kitakyusyu-shi, 808-0135 Japan;
The author is with Fukuoka Industry, Science and TechnologyFoundation, Fukuoka-shi, 814-0001 Japan;
The author is with SANYO Electric Co., Ltd, Gifu-ken, 503-0195 Japan;
The authors are with the Graduate School of Production, In-formation and Systems, Waseda University, Kitakyusyu-shi, 808-0135 Japan;
The authors are with the Graduate School of Production, In-formation and Systems, Waseda University, Kitakyusyu-shi, 808-0135 Japan;
The authors are with the Graduate School of Production, In-formation and Systems, Waseda University, Kitakyusyu-shi, 808-0135 Japan;
static timing analysis; gate delay; effective capacitance; non-iterative;
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机译:建模互连负载的有效电容以预测CMOS门斜率
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