A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme

摘要

This paper proposes a novel delay-locked loop (DLL) with fast-locking property. The improved fast-locking successive approximation register-controlled (IFSAR) scheme can decrease the locking time to n + 4 periods and be harmonic-free, where n is the bits' number of the control code for a delay line. According to the simulation result in 180nm CMOS technology, the DLL can cover the operating range from 70 MHz to 500 MHz and dissipate 10.44 mW at 500 MHz.