High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches

摘要

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 μm standard CMOS technology and the experimental results agree well with the theory.