Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel

摘要

To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time hy using the V, closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of V_(scanw), was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of V_(scanw), also.